A 1.8 to 4 GHz inductor-less highly linear CMOS LNA for wire-less receivers

Nội dung text: A 1.8 to 4 GHz inductor-less highly linear CMOS LNA for wire-less receivers

1. Nghiờn cứu khoa học cụng nghệ A 1.8 to 4 GHz inductor-less highly linear CMOS LNA for wire-less receivers Le Thi Luan1, Nguyen Huu Tho2* 1 Academy of Military Science and Technology; 2 Le Quy Don Technical University. *Corresponding author: tho.nh@mta.edu.vn Received 10 October 2021; Revised 14 November 2021; Accepted 12 December 2021. DOI: ABSTRACT This paper presents an inductor-less wide-band highly linear low-noise amplifier (LNA) for wire-less receivers. The inductor-less LNA consists of a complementary current-reuse common source amplifier combined with a low-current active feedback to obtain wide range input impedance matching and low noise figure. In our LNA, a degeneration resistor is utilized to improve linearity of the LNA. Furthermore, we designed a bypass mode for the LNA to extend the range of its applications. The proposed LNA is implemented in 28 nm CMOS process. It has a gain of 14.9 dB and a bandwidth of 2.2 GHz. The noise figure (NF) is 1.95 dB and the third- order input intercept point (IIP3) is 24.8 dBm at 2.3 GHz. It consumes 17.2 mW at a 0.9-V supply and has an area of 0.011 mm2. Keywords: Inductor-less; Current-reuse; Active feedback; Wide-band; high linearity; Low noise amplifier. 1. INTRODUCTION Nowadays, many wireless communication standards in different frequency bands have been developed for various communication applications such as 3rd generation mobile communication system (3G), long-term evolution (LTE), 5G, wire-less fidelity (Wi-Fi) and Bluetooth. Therefore, broadband receivers have become mainstream to use for mixing various standards [1-3]. In these receivers, the low noise amplifier (LNA) is an important component which plays a key role for front-end block. The wide-band LNA should satisfy some requirements, involving low noise figure (NF), great input impedance matching and high linearity. So far, many noise canceling schemes of the LNA have been implemented to achieve simultaneous wideband and low noise but not high linearity [4, 5]. Therefore, the most significant challenge of a LNA design is to ensure the linearity. The front-end of the LNA requests a high linearity to eliminate the intermodulation or cross-modulation due to the increased concurrency of adjacent blockers or transmitter on-chip leakage [6]. To overcome this challenge, a common source (CS) amplifier with current-reuse architecture and an active inductor for input matching are used in [7]. In [8], a parallel combination of common gate (CG) and CS amplifiers is realized and a resistive feedback structure is used to balance the multiple tradeoffs among NF, input matching and gain. The IIP3 in [7] and [8] obtained 5 dBm and 5.8 dBm, respectively. However, these LNAs employ an inductor in design. Consequently, the cost and die area will both be grown making these LNAs less attractive in practical applications. To overcome this problem, inductor-less LNAs are implemented in [9, 10]. These LNAs use current-reuse CS amplifier and active shunt-feedback to achieve high linearity of 12.4 dBm and 7.9 dBm in IIP3, respectively. This paper proposes an improved version of the LNA introduced [9, 10]. By using a degeneration resistor, the linearity of the LNA is enhanced. The LNA simultaneously obtains wide-band, low NF and high linearity. In addition, a bypass mode for the LNA is adopted. This paper is organized as follows. Section II introduces the architecture of the proposed inductor-less LNA. Next, in Section III, the circuit implementation is described in detail. Section IV provides the experimental results on 28 nm CMOS process followed by conclusions in Section V. Tạp chớ Nghiờn cứu KH&CN quõn sự, Số 76, 12 - 2021 11
2. Kỹ thuật điều khiển & Điện tử 2. PROPOSED ARCHITECTURE The block diagram of the proposed differential inductor-less LNA is presented in fig.1. The LNA includes two modes: LNA mode and bypass mode. The selection of the working mode for the LNA is done by the digital control bit, C. When the signal strength at the receiver input is small, the control bit C is set to ‘0’ to select the LNA mode for the amplifier. Conversely, when the received signal strength is large, the control bit is set to ‘1’ to select the bypass mode for the amplifier and the received signal is applied directly to the mixer without going through the LNA circuit. As depicted in fig. 1, capacitors C1 and C2 are used to block DC for the input and output of the LNA, respectively. In addition, C2 plays the role of matching between LNA and Mixer so the value of C2 must be chosen carefully when designing the complete front-end circuit with mixer following the LNA circuit. The proposed LNA employs degeneration resistor to improve the linearity of the circuit where the value of the resistor can be varied so that the circuit achieves a wide range of values of IIP3 to counteract the influence of process, voltage and temperature (PVT). To do this, four digital control bits B0-B3 are used to select the resistor value in the LNA circuit. C Bypass S2 mode S1 VDD DC Blocker C 1 C2 IN+ LNA to Mixer C 1 C2 IN- DC Blocker and match B0-B3 to Mixer Fig 1. Block diagram of the proposed inductor-less LNA. 3. CIRCUIT DESCRIPTION 3.1. Proposed LNA The proposed LNA is illustrated in fig. 2. It includes a main amplifier (A) and a shunt feedback path (F). VDD A lD M1 Vin RF Vout CL CPAD M2 VDD R1 M3 RS VDD M4 F R2 RD Fig. 2. Circuit implementation of the proposed LNA. 12 L. T. Luan, N. H. Tho, “A 1.8 to 4 GHz inductor-less highly linear for wire-less receivers.”
3. Nghiờn cứu khoa học cụng nghệ The main amplifier bases on a current-reuse structure with PMOS and NMOS pairs connected in series. This is a self-bias structure in which PMOS and NMOS are biased by the D terminal voltage of M1 and M2 through the RF resistor. By using current-reuse structure, transconductance is boosted and the LNA achieves high gain and low NF simultaneously. The active feedback loop using source follower structure enables a wideband matching and ensures a high linearity of the LNA. A degeneration resistor (RD) which can be changed is added to enhance linearity of the LNA. The S terminal voltage of M1 and the bias voltage for M4 are connected to the power supply (VDD) of the LNA to eliminate the need for Band gap reference circuits outside of the LNA circuit. As a result, the total area occupied by the LNA circuit is reduced. The circuit analysis in this section is performed based on [9] with the results summarized to serve the design of the LNA. The architecture of the LNA circuit in fig. 2 is modeled by fig. 3 for simplicity in calculating the formulas. In which Gm1 and Gm2 are transconductance of current-reuse structure (A) and source follower structure (F), respectively. Then, Gm1 and Gm2 are given by (1) (2) -Gm1 1 2 ZS Vin Vout Z Zin Z1 2 +Gm2 Fig. 3. Modeling of LNA in Fig. 2. The input parasitic impedance is: 11 Z1 (3) gds3 g ds 4 s() C pad C gs 2 C sb 3 C db 4 Feedback structure’s impedance is: 1 ZRSF (4) s() Cgd23 C gs Output impedance is: 11 Z2 (5) gds2 s() C L C gd 3 C db 2 where gdsi is output conductance of the device Mi; Cgsi, Cgdi, Cdbi, Csbi are the intrinsic parasitic capacitances of device Mi; Cpad is the input pad capacitance and CL is the load capacitance. The voltage gain of the LNA is given by Tạp chớ Nghiờn cứu KH&CN quõn sự, Số 76, 12 - 2021 13
4. Kỹ thuật điều khiển & Điện tử (6) If ZS >> Z2, (6) is reduced to (7) Expression (7) reveals that the gain of the LNA circuit strongly depends on the A stage. The input impedance of the LNA is determined by (8) If the bias resistor RF of block A is large enough and ggdsds34 0 , then substituting (3), (4) and (5) in (8), the input impedance is calculated by the formula 1 gRmS3 Zin (9) gAmV3 1 Expression (9) presents that wide-band input impedance matching could be achieved by adjusting and optimizing the gain (AV), feedback resistor (RS) and M3 transistor (gm3) of the LNA. In which RS must be chosen small enough to keep broadband impedance matching. The main noise distribution of the LNA comes from the MOS devices (M1, M2, M3, M4), feedback resistor (RS) and bias resistor (RF). Noise factor of each element in block A can be expanded as (10) (11) (12) And noise factor of each element in block F can be expanded as (13) (14) 2 g n R R m3 (15) RSBS 2 (1 gRmS3 ) where RB is the signal source resistance,  is the thermal noise excess factor, and gdo is the output transconductance at VDS = 0V. Expressions (10-15) show that circuit A is the dominant noise component of the LNA [9]. As a result, a low-noise design for circuit A is required to achieve a low-noise LNA. This can be realized by choosing large bias resistors and large size of the MOS devices M1, M2. 3.2. Control IIP3 of LNA Fig.4 presents the implemented diagram of proposed IIP3 control circuit for the LNA. As mentioned early, a degeneration resistor is added into the feedback stage to enhance the linearity of the LNA. To achieve a wide range of values of IIP3, four digital control bits, B0, B1, B2, B3, are used in this work. 14 L. T. Luan, N. H. Tho, “A 1.8 to 4 GHz inductor-less highly linear for wire-less receivers.”
5. Nghiờn cứu khoa học cụng nghệ IFB VDD M4 R2 B0 B1 B2 B3 R3 R4 R5 R6 Fig. 4. Control IIP3 by digital logic. Degeneration resistor values are selected when the control bit is high logic level and disconnected from the circuit when the control bit is low logic level. Therefore, the four control bits select 16 possible values of the degeneration resistor and respectively generate 16 feedback current values (table I) for the feedback stage. Feedback current value is designed from 0.08 mA to 1.2 mA with 80 àA linear increments. This is done by selecting the values R3, R4, R5, R6 so that the corresponding feedback current is 0.08 mA (B0 = 1, B1 = 0, B2 = 0, B3 = 0), 0.16 mA (B0 = 0, B1 = 1, B2 = 0, B3 = 0), 0.32 mA (B0 = 0, B1 = 0, B2 = 1, B3 = 0) and 0.64 mA (B0 = 0, B1 = 0, B2 = 0, B3 = 1). The size of the NMOSs for digital control must be not small to minimize their noise contribution to the whole circuit. Table I. Feedback current values corresponding to the control bits. B3 B2 B1 B0 IFB (mA) 0 0 0 1 0.08 0 0 1 0 0.16 0 0 1 1 0.24 0 1 0 0 0.32 0 1 0 1 0.4 0 1 1 0 0.48 0 1 1 1 0.56 1 0 0 0 0.64 1 0 0 1 0.72 1 0 1 0 0.8 1 0 1 1 0.88 1 1 0 0 0.96 1 1 0 1 1.04 1 1 1 0 1.12 1 1 1 1 1.2 3.3. Bypass mode In this work, the LNA circuit with bypass mode is designed to increase its application range. A switch is used to make the bypass mode as shown in fig. 5. The mode selection for LNA is performed by switching the values of the digital control bit C. C = ‘0’, select LNA mode; C = ‘1’, select bypass mode. Tạp chớ Nghiờn cứu KH&CN quõn sự, Số 76, 12 - 2021 15
6. Kỹ thuật điều khiển & Điện tử C M1 IN OUT M2 C Fig. 5. Switch circuit for bypass mode of the LNA. The switch designing must be executed carefully to both ensure the quality of the LNA circuit in bypass mode and does not affect the quality of the LNA circuit in the amplification mode. 3.4. LNA design process After analyzing the circuit in Section A, in this Section, we present a design process for the proposed inductor-les LNA circuit. This process simplifies the design of the LNA and can be used as a reference for the design of other LNAs. There are 7 steps to design the LNA as follow. Step 1: Design the block A in fig. 2. Select the widths of M1 and M2 (equal widths) to get large Gm (using formula (1)) and low NF (Equation 10-11). Choose a value of RF large enough to ensure the gain and noise of the block A. Design M1 and M2 in the saturation region so that the circuit works stably under the influence of PVT. Step 2: Connecting the block F with an ideal current source (to generate IFB), the initialization value of IFB is less than 1 mA to save power and reduce noise from the block F to the whole circuit. Then, select gm3 value and RB value. Step 3: Check the NF of the whole circuit. Reduce IFB if NF does not meet the target. The IFB must not be reduced too small because then the influence of the resistor Rs on the impedance matching will be limited. Change gm3 and Rs to perform impedance matching according to formula (9). Adjust the RF resistor so that the gain is satisfactory. Test S11 with respect to the value of the RF resistor. Because IFB also affects S11 so RB is preferred to achieve the target gain. Step 4: Determine IFB: Measure OIP3 and IIP3 to check that with the selected values for M1, M2, RF of block A, in what range the IFB will meet the requirements of IIP3, OIP3. Step 5: Check again the impedance matching (S11) when changing the IFB because there is a constraint between the wideband matching and the linearity of the circuit. In step 3, if the reduction of IFB is no longer reasonable, we increase Gm1 to ensure that M1 and M2 are in the saturation region. Repeat from step 2 until NF and S11 reach the target. Step 6: Replace the ideal current source by a digital control circuit to improve the linearity of the LNA. Step 7: Design switch for bypass mode of the LNA. The switching circuit parameters are calculated carefully selected to optimize the quality of the LNA circuit in Bypass mode and LNA mode. After following the steps in the LNA design, we obtain the values of the parameters in the LNA circuit as shown in table II. Table II. Design parameter values in the LNA. M1 180àm/30àm M2 180àm/30àm M3 60àm/30àm M4 45àm/30àm RF 4.1 kΩ RS 210 Ω 16 L. T. Luan, N. H. Tho, “A 1.8 to 4 GHz inductor-less highly linear for wire-less receivers.”
7. Nghiờn cứu khoa học cụng nghệ 4. SIMULATION RESULTS AND DISCUSSION Based on the previous analysis, a 1.8 to 4 GHz LNA is designed. The proposed differential inductor-less LNA is implemented in a 28 nm CMOS process. The layout picture of the LNA is presented in fig. 6. It occupies an area of 0.011 mm2 without the Pads. The power consumption is 17.2 mW at the supply voltage of 0.9 V. Fig. 6. Layout of the LNA. Fig. 7. Post-layout simulation result of S21. Tạp chớ Nghiờn cứu KH&CN quõn sự, Số 76, 12 - 2021 17
8. Kỹ thuật điều khiển & Điện tử Fig. 8. Post-layout simulation result of S11. Fig. 9. Post-layout simulation result of NF. Fig. 10. Post-layout simulation result of IIP3. Post-layout simulation results are depicted in fig.7 - fig.10. fig. 7 shows the power gain (S21) of the LNA. S21 is always greater than 14 dB in full operation range, 1.8 GHz – 4 GHz, and the flatness of the gain is approximately 0.06 dB per 100 MHz. This result shows that the proposed LNA architecture can be used in front-end circuits for direct conversion receivers where it requests wide baseband bandwidth as LTE or 5G. Input reflection coefficient (S11) qualifies the input impedance matching and S11 is below -10 dB in the frequency band of interest as shown in fig. 8. Therefore, the LNA could obtain greatly input impedance matching. The lowest NF that LNA achieved is 1.65 dB as illustrated in fig. 9 and NF increases by 1.95 dB when the frequency reaches 4 GHz. 18 L. T. Luan, N. H. Tho, “A 1.8 to 4 GHz inductor-less highly linear for wire-less receivers.”
9. Nghiờn cứu khoa học cụng nghệ The third order interception point is measured in a two-tone manner. The two input signals are separated at 1 MHz away. Fig. 10 shows the IIP3 result. IIP3 obtains 24.8 dBm at 2.3 GHz. IIP3 performance can be controlled by bits B0-B3 to overcome the influence of the PVT. This result indicates that the addition of degeneration resistor to the feedback stage has considerably enhanced the linearity of the proposed LNA. Table III benchmarks the performances with the prior art. This work has low NF, high linearity with trade-off of power. Table III. Performance Comparison of LNA. [7] [9] [11] This work (measure) (measure) (simulation) (post-simulation) Technology 130 CMOS 130 110 28 (nm) CMOS CMOS CMOS Supply (V) 1.4 1.5 1.2 0.9 BW (GHz) 3.9 2 2 2.2 Inductor Yes No No No S11 (dB) < -10 < -10 < -10 < -10 S21 dB) 10.8 19.2 7.9 14.9 NF dB) 3.5 2.4 3.3 1.95 IIP3 (dBm) -1.6 8.6 3.7 24.8 Area (mm2) 0.18 0.014 N/A 0.011 Power (mW) 6.16 3.11 3.24 17.2 5. CONCLUSION The proposed inductor-less LNA is implemented in 28 nm CMOS process. The LNA achieves wide-band, low-noise, smal gain variation across the working bandwidth and high linearity by combining current-reuse structure and active feedback structure. A degeneration resistor is added into the feedback structure to enhance IIP3 to 24.8 dBm in post-simulation, outperforming other published schemes. In future work, we will completely design a RF Front- end circuit for direct conversion receiver including proposed inductor-less LNA. Acknowledgement: This research is supported by fund and CAD tool from Viettel IC Design Center. REFERENCES [1]. R. Bagheri, et al., “An 800-MHz–6-GHz software-defined wireless receiver in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2860–2876, Dec. 2006. [2]. A. Geis, et al., “A 0.5 mm2 power-scalable 0.5–3.8-GHz CMOS DT-SDR receiver with second-order RF band-pass sampler,” IEEE J. Solid-State Circuits, vol. 45, no. 11, pp. 2375–2387, Nov. 2010. [3]. R. Chen and H. Hashemi, “A 0.5-to-3 GHz software-defined radio receiver using discrete-time RF signal processing,” IEEE J. Solid-State Circuits, vol. 49, no. 5, pp. 1097–1111, May 2014. [4]. B. G. Perumana, et al. “Resistive-Feedback CMOS Low-Noise Amplifiers for Multiband Applications,” IEEE Transactions on Microwave Theory and Techniques, Vol. 56, No. 5, May 2008. [5]. S. S. Regulagadda, et al., "A Packaged Noise-Canceling High-Gain Wideband Low Noise Amplifier," IEEE Trans. Circuits Syst. II: Express, DOI 10.1109/TCSII.2018.2828781, 2018. [6]. A. Pọrssinen, “System design for multi-standard radios,” in IEEE ISSCC Girafe Forum, Feb. 2006. [7]. Ting Ma and Feng Hu, “A Wideband Flat Gain Low Noise Amplifier Using Active Inductor For Input Matching,” IEEE Trans. Circuits Syst. II: Express, DOI 10.1109/TCSII.2018.2872068, 2018. [8]. H. Yu, et al., “A 0.096-mm2 1–20-GHz Triple-Path Noise-Canceling Common-Gate Common-Source LNA With Dual Complementary pMOS–nMOS Configuration,” IEEE Transactions on Microwave Theory and Techniques, DOI 10.1109/TMTT.2019.2949796, 2019. [9]. R M. De Souza, A. Mariano, and T. Taris, “Reconfigurable inductorless wideband CMOS LNA for wireless communications,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 64, no. 3, pp. 675–685, Mar. 2017. Tạp chớ Nghiờn cứu KH&CN quõn sự, Số 76, 12 - 2021 19
10. Kỹ thuật điều khiển & Điện tử [10]. G. Guitton, et al., “Design Methodology Based on the Inversion Coefficient and Its Application to Inductorless LNA Implementations,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 66, no. 10, Oct. 2019. [11]. W. Shen, P. Liu, and S. Zhang, “An Inductor-less Highly Linear LNA with Noise Cancelling and Current Reusing for 3-5 GHz Low-Power UWB Receivers,” ICSICT, 2020. TểM TẮT MẠCH CMOS LNA 1.8 ĐẾN 4 GHz TUYẾN TÍNH CAO KHễNG SỬ DỤNG CUỘN CẢM CHO MÁY THU Vễ TUYẾN Bài bỏo này trỡnh bày về mạch khuếch đại tạp õm thấp (LNA) cú độ tuyến tớnh cao, dải rộng, khụng sử dụng cuộn cảm cho cỏc mỏy thu vụ tuyến. LNA khụng cú cuộn cảm bao gồm một bộ khuếch đại cấu trỳc nguồn chung sử dụng lại dũng kết hợp với một mạch phản hổi tớch cực dũng thấp để đạt được phối hợp trở khỏng đầu vào dải rộng và tạp õm thấp. Trong LNA, chỳng tụi đề xuất sử dụng kỹ thuật điện trở suy giảm để cải thiện độ tuyến tớnh của mạch. Thờm vào đú, chỳng tụi thiết kế chế độ đi vũng cho mạch LNA để mở rộng phạm vi ứng dụng của mạch. LNA đề xuất được thực hiện trờn cụng nghệ CMOS 28 nm. LNA cú hệ số khuếch đại 14.9 dB và băng thụng 2.2 GHz. Hệ số tạp õm (NF) là 1.95 dB và điểm chặn đầu vào bậc 3 (IIP3) là 24.8 dBm tại 2.3 GHz. Mạch tiờu thụ 17.2 mW với nguồn cung cấp 0.9 V và cú diện tớch chiếm trờn chip là 0.011 mm2. Từ khúa: Khụng sử dụng cuộn cảm; Sử dụng lại dũng; Phản hồi tớch cực; Dải rộng; Độ tuyến tớnh cao; Khuếch đại tạp õm thấp. 20 L. T. Luan, N. H. Tho, “A 1.8 to 4 GHz inductor-less highly linear for wire-less receivers.”