Digital Design with the Verilog HDL - Chapter 0: Introduction

Nội dung text: Digital Design with the Verilog HDL - Chapter 0: Introduction

1. Digital Design with the Verilog HDL Chapter 0: Introduction Dr. Phạm Quốc Cường Computer Engineering – CSE – HCMUT 1
2. Instructor & TAs • Instructor: – Dr. Phạm Quốc Cường – cuongpham@hcmut.edu.vn – www.cse.hcmut.edu.vn/~cuongpham • TA: – Kiều Đỗ Nguyên Bình – Trần Thị Thùy Châu 2
3. About System Architecture - Dr. Cuong Pham- Quoc
4. About System Architecture - Dr. Cuong Pham- Quoc
5. About System Architecture - Dr. Cuong Pham- Quoc
6. The Digital System Course • Paper-and-Pencil Design • What are disadvantages? – – – 6
7. HDL • Q: What is HDL? • A: Hardware Description Language used to describe hardware components 7
8. HDL (cont.) • Definition: – Computer language (not a programming language) – Describe structure and operation of a digital circuit – Simulate and verify a digital circuit 8
9. HDL (cont.) • Advantages: – Manage large and complex circuits easily – Portable and technology-independence – Reuse predefine modules – Automated synthesized circuit • VerilogTM & VHDL – IEEE standard – Supported by synthesis tools for both ASICs and FPGA 9
10. The Course • Contents: – Combinational circuits design with the Verilog HDL – Sequential circuits design with the Verilog HDL – Simulation and errors check – State transaction machine – Digital circuits design with the Verilog HDL – Memory design with the Verilog HDL – Clock generation 10
11. Course Outcomes • Using the Verilog HDL to design combinational and sequential digital circuits • Analyzing and modeling problems by state- transaction-machine • Using simulation and synthesis tools to verify designed circuits 11
12. Learning Materials • Slides: www.cse.hcmut.edu.vn/~cuongpham or BKeL • Textbooks 12
13. Assessment • Lab & Project: 30% (TA: Tran Thi Thuy Chau) • Active learning (presentation): 10% (mandatory) • Mid-term: 20% – multiple choices, closed books • Final exam: 40% – multiple choices, closed books 13