Digital Design with the Verilog HDL - Chapter 1: Digital Design Review

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1. Digital Design with the Verilog HDL Chapter 1: Digital Design Review Dr. Phạm Quốc Cường Computer Engineering – CSE – HCMUT 1
2. Technology Tradeoffs Full-Custom Market Volume IC to Amortize Standard Cells Time to Prototype FPGAs, Gate Arrays PLDs Non-Recurring Engineering (NRE) Cost Process complexity Density, speed, complexity 2
3. Design Methodology Design Integration Post-Synthesis Design Specification Extract Parasitics and Verification Timing Verification 1 5 9 13 Pre-Synthesis Test Generation and Design Partition Design Sign-Off Sign-Off Fault Simulation 2 6 10 14 Design Entry: Cell Placement, Scan Synthesize and Map Verilog Behavioral Chain and Clock Tree Production-Ready Gate-Level Netlist 3 Modeling 7 11 Insertion, Cell Routing Masks Simulation / Post-Synthesis Verify Physical and Functional Design Validation Electrical Design Rules 4 Verification 8 12 Verilog-based 3
4. Combinational – Sequential Logic a • Combinational logic: y1 – The outputs at any time, b Combinational y2 t, are a function of only c Logic the inputs at time t d y3 • Sequential logic: – The outputs at time t are a y1 a function of the inputs b Sequential y2 at time t and the c outputs at time t-1 Circuit y3 4
5. Transistor • nMos • pMos 5
6. CMOS Technology pMos Pull-up • Complementary metal- network oxide semiconductor Input Output • Outputs are always either 0 or 1 nMos Pull-down network Invert gate NAND gate NOR gate 6
7. Parallel and Serial • nMOS: 1 = ON • Series: all transistors • pMOS: 0 = ON are on a a a a a • Parallel: at least one 0 0 1 1 g1 transistor is on g2 a 0 1 0 1 a a a a b b b b b g1 g2 0 0 0 1 1 0 1 1 (a) OFF OFF OFF ON b b b b b a a a a a (c) OFF ON ON ON 0 0 1 1 g1 g2 a 0 1 0 1 a a a a b b b b b g1 g2 0 0 0 1 1 0 1 1 (b) ON OFF OFF OFF b b b b b (d) ON ON ON OFF7
8. The “Conduction Complement” Rule • CMOS gate’s output is always either 0 or 1 Y • For example: NAND A – Y=0 if and only if both inputs are 1 B – Y=1 if and only at least one input is 0 – pMos transistors are parallel while nMos transistors are serial • The “Conduction Complements” rule – The pull-up network always complements the pull-down network – Parallel → Serial, Serial → Parallel 8
9. CMOS Inverter A Y VDD 0 1 A Y A Y GND 9
10. CMOS Inverter A Y VDD 0 1 0 OFF A=1 Y=0 ON A Y GND 10
11. CMOS Inverter A Y VDD 0 1 1 0 ON A=0 Y=1 OFF A Y GND 11
12. CMOS NAND Gate A B Y 0 0 0 1 Y 1 0 A 1 1 B 12
13. CMOS NAND Gate A B Y ON 0 0 1 ON 0 1 Y=1 A=0 1 0 OFF 1 1 B=0 OFF 13
14. CMOS NAND Gate A B Y ON 0 0 1 OFF 0 1 1 Y=1 A=0 1 0 OFF 1 1 B=1 ON 14
15. CMOS NAND Gate A B Y 0 0 1 ON OFF 0 1 1 Y=1 A=1 1 0 1 ON 1 1 B=0 OFF 15
16. CMOS NAND Gate A B Y 0 0 1 OFF OFF 0 1 1 Y=0 A=1 1 0 1 ON B=1 1 1 0 ON 16
17. CMOS NOR Gate A B Y 0 0 1 A 0 1 0 1 0 0 B 1 1 0 Y 17
18. 3-input NAND Gate • Y is 0 if and only if ALL inputs are 1 • Y is 1 if and only if AT LEAST one input is 0 Y A B C 18
19. Design CMOS Gates • Example: – Using the CMOS Technology, draw transistor structure of a 4-input NOR gate A B C D Y 19
20. Design CMOS Gate (cont.) • Example 2 (Homework): – Using the CMOS Technology, draw transistor structure of a 4-input NAND gate 20
21. Compound Gates • Compound gates: can describe any inverter function (not function) 21
22. Example: AOI22 Y = ( A• B) + (C • D) A C A C B D B D (a) (b) C D A B C D A B (c) (d) C D A A B B Y Y C A C D B D (f) (e) 22
23. AOI22 • Use AND/OR gate to implement? – 20 transitors 23
24. Example: O3AI Y= (A + B + C) • D A B C D Y D A B C 24
25. Standard Cells • Library of common gates and structures (cells) • Decompose hardware in terms of these cells • Arrange the cells on the chip • Connect them using metal wiring 25
26. FPGAs • “Programmable” hardware • Use small memories as truth tables of functions • Decompose circuit into these blocks • Connect using programmable routing • SRAM bits control functionality FPGA Tiles P1 P2 P P3 P4 OUT P5 P6 P7 P8 I1 I2 I3 26