Digital Design with the Verilog HDL - Chapter 6: FSM with Verilog

Nội dung text: Digital Design with the Verilog HDL - Chapter 6: FSM with Verilog

1. Digital Design with the Verilog HDL Chapter 6: FSM with Verilog Dr. Phạm Quốc Cường Computer Engineering – CSE – HCMUT 1
2. Explicit State Machines • Declare registers to store explicit states • Combination logic circuit controls states • Verilog: – Edge-trigger behaviour synchronizing the states – Level-trigger behaviour describing the next states and output logic 2
3. Mealy machine vs. Moore machine Block Diagram of a Mealy sequential machine Block Diagram of a Moore sequential machine 3
4. BCD to Excess-3 Converter - FSM Next state/Output table Next state/output State input 0 1 S_0 S_1/1 S_2/0 S_1 S_3/1 S_4/0 S_2 S_4/0 S_4/1 S_3 S_5/0 S_5/1 S_4 S_5/1 S_6/0 S_5 S_0/0 S_0/1 S_6 S_0/1 -/- State transition graph State transition table 4
5. BCD to Excess-3 Converter - Verilog module BCD_to_Excess3(B_out, B_in, clk, reset); input B_in, clk, reset; output B_out; parameter S_0 = 3’b000, //state encoding S_1 = 3’b001, S_2 = 3’b101, S_3 = 3’b111, S_4 = 3’b011, S_5 = 3’b110, S_6 = 3’b010, dont_care_state = 3’bx, dont_care_out = 1’bx; reg [2:0] state, next_state; reg B_out; always @(posedge clk, negedge reset) //edge-trigger behaviour if (reset == 1’b0) state <= S_0; else state <= next_state; 5
6. BCD to Excess-3 Converter - Verilog always @(state, B_in) begin B_out = 0; case (state) S_0: if (B_in == 1’b0) begin next_state = S_1; B_out = 1’b1; end else if (B_in == 1’b1) next_state = S_2; S_1: if (B_in == 1’b0) begin next_state = S_3; B_out = 1’b1; end else if (B_in == 1’b1) next_state = S_4; S_2: S_3: S_4: S_5: S_6: endcase end 6
7. Synthesized Circuit Phát biểu case không đủ tất cả các trường hợp 7
8. BCD to Excess-3 Converter - Verilog always @(state, B_in) begin B_out = 0; case (state) S_0: if (B_in == 1’b0) begin next_state = S_1; B_out = 1’b1; end else if (B_in == 1’b0) next_state = S_2; S_1: if (B_in == 1’b0) begin next_state = S_3; B_out = 1’b1; end else if (B_in == 1’b0) next_state = S_4; S_2: S_3: S_4: S_5: S_6: default: next_state = dont_care_state; endcase end 8
9. Synthesized Circuit 9
10. Sequence Recognizer: Mealy module Seq_Rec_3_1s_Mealy (output D_out, input D_in, En, clk, reset); parameter S_idle = 0, S_0 = 1, S_1 = 2, S_2 = 3; // Binary code reg [1: 0] state, next_state; always @ (negedge clk) Recommended Style! if (reset == 1) state <= S_idle; else state <= next_state; always @ (state, D_in, En) begin case (state) S_idle: if ((En == 1) && (D_in == 1)) next_state = S_1; else if ((En == 1) && (D_in == 0)) next_state = S_0; else next_state = S_idle; S_0: if (D_in == 0) next_state = S_0; else if (D_in == 1) next_state = S_1; else next_state = S_idle; S_1: if (D_in == 0) next_state = S_0; else if (D_in == 1) next_state = S_2; else next_state = S_idle; S_2: if (D_in == 0) next_state = S_0; else if (D_in == 1) next_state = S_2; else next_state = S_idle; default: next_state = S_idle; endcase end assign D_out = ((state == S_2) && (D_in == 1 )); // Mealy output endmodule
11. Sequence Recognizer: Mealy – Synthesized Circuit aoi21_a reset_b dffrpb_a dffrpb_a inv_a clk and2i_a nor2_a En aoi211_a and3_a D_out inv_a dffrpb_a esdpupd D_in
12. Sequence Recognizer: Mealy – Synthesized Circuit 12
13. Sequence Recognizer: Moore module Seq_Rec_3_1s_Moore (output D_out, input D_in, En, clk, reset); parameter S_idle = 0, S_0 = 1, S_1 = 2, S_2 = 3, S_3 = 4; Prevent accidental reg [2: 0] state, next_state; latches! always @ (negedge clk) if (reset == 1) state <= S_idle; else state <= next_state; always @ (state or D_in) begin next_state = S_idle; case (state) S_idle: if ((En == 1) && (D_in == 1)) next_state = S_1; else if ((En == 1) && (D_in == 0)) next_state = S_0; // else next_state = S_idle; // Remove! S_0: if (D_in == 0) next_state = S_0; else if (D_in == 1) next_state = S_1; // else next_state = S_idle; S_1: if (D_in == 0) next_state = S_0; else if (D_in == 1) next_state = S_2; // else next_state = S_idle; S_2, S_3: if (D_in == 0) next_state = S_0; else if (D_in == 1) next_state = S_3; // else next_state = S_idle; default: next_state = S_idle; // Why not 3'bx? endcase end assign D_out = (state == S_3); // Moore output endmodule
14. Sequence Recognizer: Moore Synthesize Circuit and2i_a mux2_a nand2_a En reset aoi211_a D_in inv_a inv_a dffrpb_a inv_a aoi211_a inv_a clk nor2_a nor2_a dffrpb_a nand2_a inv_a dffrpb_a D_out esdpupd CSE/EE 40462 FSMs, Datapath Controllers.14
15. Mealy machine vs. Moore machine Block Diagram of a Mealy sequential machine Block Diagram of a Moore sequential machine 15
16. Simulation Results Mealy Valid output Mealy glitch glitch 16
17. Registered Output 17
18. Registered Output Mealy Type Moore Type 18