Digital Design with the Verilog HDL - Chapter 8: Datapath & Controller

Nội dung text: Digital Design with the Verilog HDL - Chapter 8: Datapath & Controller

1. Digital Design with the Verilog HDL Chapter 8: Datapath & Controller Dr. Phạm Quốc Cường Computer Engineering – CSE – HCMUT 1
2. Digital Systems Classification • Control-dominated: – Reactive systems responding to external events • Data-dominated: – High throughput data computation and transport => Sequential machines are classified and portioned into datapath units and control units 2
3. Control vs. Datapath • Control units: – FSM coordinating the execution of instructions that perform operation on the datapath • Datapath units: – Computational resources (ALU, register, ) – Adder, multiplier – DSP – 3
4. State-machine Controller and Datapath 4
5. Controller and Datapath Modelling Modelling Functional • Controller: • Controller: – State transaction graphs – Generate signals: load, read, – Algorithmic-state machine clear, and shift storage (ASM) registers • Datapath: – Control the operations: ALU, complex datapath units – Data flow graph • Datapath: – Perform operations 5
6. Design Example: Binary Counter module binary_counter (Count, enable, clk, rst); output [3: 0] Count; input enable, clk, rst; reg [3: 0] Count; always @ (posedge rst or posedge clk) begin if (rst == 1'b1) Count <= 3'b0; else if (enable == 1'b1) Count <= Count + 1’b1; else Count <= Count; end endmodule 6
7. Design Example: Binary Counter • What should we do if count <= count + 1’b1 after 3 clock cycles? 7
8. Architecture for Binary Counter enable_dp 8
9. Binary Counter: Datapath & Controller module Binary_Counter_Part_RTL (count, enable, clk, rst); parameter size = 4; output [size -1: 0] count; input enable; input clk, rst; wire enable_DP; Control_Unit M0 (enable_DP, enable, clk, rst); Datapath_Unit M1 (count, enable_DP, clk, rst); endmodule 9
10. Binary Counter: Controller module Control_Unit (enable_DP, enable, clk, rst); output enable_DP; input enable; input clk, rst;// Not needed wire enable_DP = enable; // what should we do for counter after 3 clock cycles endmodule 10
11. Binary Counter: Datapath module Datapath_Unit (count, enable, clk, rst); parameter size = 4; output [size-1: 0] count; input enable, clk, rst; reg [size-1: 0]count; always @ (posedge clk) if (rst == 1) count <= 4'b0000; else if (enable == 1) count <= next_count(count); function [size-1: 0] next_count; input [size-1:0] count; begin next_count = count + 4'b0001; end endfunction endmodule 11
12. Combinational Binary Multiplier Multiplicand 1 1 0 1 0 1 1 1 21510 Multiplier 0 0 0 1 0 1 1 1 2310 Shift copies of 1 1 0 1 0 1 1 1 the multiplicand 1 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 Double shift 1 0 0 1 1 0 1 0 1 0 0 0 1 494510 • A combinational Circuit can be developed to implement the product • Require hardware with multiple adders for each column • Ordinary adder operates on only two words at a time 12
13. Combinational Binary Multiplier Multiplicand 1 1 0 1 0 1 1 1 21510 Multiplier 0 0 0 1 0 1 1 1 2310 1 1 0 1 0 1 1 1 Accumulated Shift copies of Partial Products 1 1 0 1 0 1 1 1 the multiplicand 1 0 1 0 0 0 0 1 0 1 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 0 1 0 1 1 1 Double shift 1 0 0 1 1 0 1 0 1 0 0 0 1 494510 • Combinational Binary Multiplier operate fast, but require a significant amount of silicon area 13
14. Sequential Binary Multiplier • Choose a datapath architecture • Design state machine for controller Word1 Word2 [-:0] [-:0] 15 7 0 Start 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 product 7 0 Ready 16 Sequential + 0 0 0 1 0 1 1 1 multiplier Binary 15 7 0 Multiplier Clock 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 multiplicand Reset Datapath architecture of sequential 8-bit multiplier Products [-:0] Interface signals and block diagram 14
15. Register transfers product 7 0 multiplier 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 15 7 multiplicand 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 + 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 Shift Multiplicant 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 0 + 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 1 Shift Multiplicant 0 0 0 0 0 0 1 1 0 1 0 1 1 1 0 0 + 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 1 1 0 0 0 0 1 Shift Multiplicant 0 0 0 0 0 1 1 0 1 0 1 1 1 0 0 0 Not add 15
16. Structural Units • Top-level module: Multiplier_STG_0 • m0: LSB of Multiplier, used to control state transaction word1 word2 Load_words Start m0 Shift Add Controller Datapath Clock Reset m0 Ready Product 16
17. STGs for 4-bit Seq. Multiplier !Reset/ !Reset/ Reset Reset Ready S_Idle Ready S_Idle Start/Load_word, Start/Load_word, Ready Start/Load_word, Ready S_1 Ready S_1 [0]/Add [0]/Add S_8 S_8 S_2 S_2 Ready Ready ![0] ![0]/shift ![0] ![0]/shift [0]/Add -/Shift [0]/Add -/Shift S_7 S_7 S_3 S_3 -/Shift ![0]/Shift ![0]/Shift -/Shift ![0]/Shift ![0]/Shift [0]/Add [0]/Add S_6 S_6 S_4 S_4 [0]/Add S_5 [0]/Add S_5 -/Shift -/Shift 17
18. Module Decleration module Multiplier_STG_0 (product, Ready, word1, word2, Start, clock, reset); parameter L_word = 4; // Datapath size output [2*L_word -1: 0] product; output Ready; input [L_word -1: 0] word1, word2; input Start, clock, reset; wire m0, Load_words, Shift; Datapath M1 (product, m0, word1, word2, Load_words, Shift, Add, clock, reset); Controller M2 (Load_words, Shift, Add, Ready, m0, Start, clock, reset); endmodule 18
19. Controller module Controller (Load_words, Shift, Add, Ready, m0, Start, clock, reset); parameter L_word = 4; // Datapath size parameter L_state = 4; // State size output Load_words, Shift, Add, Ready; input m0, Start, clock, reset; reg [L_state -1: 0] state, next_state; parameter S_idle = 0, S_1 = 1, S_2 = 2; parameter S_3 = 3, S_4 = 4, S_5 = 5, S_6 = 6; parameter S_7 = 7, S_8 = 8; reg Load_words, Shift, Add; wire Ready = ((state == S_idle) && !reset) || (state == S_8); always @ (posedge clock or posedge reset) // State transitions if (reset) state <= S_idle; else state <= next_state; 19
20. always @ (state or Start or m0) begin // Next state and control logic Load_words = 0; Shift = 0; Add = 0; case (state) S_idle: if (Start) begin Load_words = 1; next_state = S_1; end else next_state = S_idle; S_1: if (m0) begin Add = 1; next_state = S_2; end else begin Shift = 1; next_state = S_3; end S_2: begin Shift = 1; next_state = S_3; end S_3: if (m0) begin Add = 1; next_state = S_4; end else begin Shift = 1; next_state = S_5; end S_4: begin Shift = 1; next_state = S_5; end S_5: if (m0) begin Add = 1; next_state = S_6; end else begin Shift = 1; next_state = S_7; end S_6: begin Shift = 1; next_state = S_7; end S_7: if (m0) begin Add = 1; next_state = S_8; end else begin next_state = S_8; end S_8: if (Start) begin Load_words = 1; next_state = S_1; end else next_state = S_8; default: next_state = S_idle; endcase end endmodule 20
21. Datapath (1) module Datapath (product, m0, word1, word2, Load_words, Shift, Add, clock, reset); parameter L_word = 4; output [2*L_word -1: 0] product; output m0; input [L_word -1: 0] word1, word2; input Load_words, Shift, Add, clock, reset; reg [2*L_word -1: 0] product, multiplicand; reg [L_word -1: 0] multiplier; wire m0 = multiplier[0]; 21
22. Datapath (2) always @ (posedge clock or posedge reset) begin if (reset) begin multiplier > 1; multiplicand <= multiplicand << 1; end else if (Add) product <= product + multiplicand; end endmodule 22