Designing SPI to I2C Protocol Converter Base on ASIC Technology and Implementing on the FPGA Platform

Nội dung text: Designing SPI to I2C Protocol Converter Base on ASIC Technology and Implementing on the FPGA Platform

1. JST: Smart Systems and Devices Volume 31, Issue 2, September 2021, 019-026 Designing SPI to I2C Protocol Converter Base on ASIC Technology and Implementing on the FPGA Platform Nguyen Hoang Dung Hanoi University of Science and Technology, Hanoi, Viet Nam *Email: dung.nguyenhoang@hust.edu.vn Abstract Nowadays embedded systems are using a lot of different communication standards to transfer data such as USB, UART, SPI, I2C, etc. To be able to transfer data with each communication standard, the system needs at least one controller block for that communication standard. This has added to the complexity of the system and the cost of manufacturing hardware. Embedded systems only support SPI communication if desired, which can still be communicated with peripherals with I2C standard. However, the SPI cannot be directly connected to the I2C but must use a standard communication converter. This paper will primarily focus on designing an IP core communication standard converter from SPI to I2C using APB (Advanced Peripheral Bus) communication as one of the AMBA (Advanced Microcontroller Bus Architecture) communication sets. In particular, APB is a bus used to communicate with peripherals that do not require fast processing speeds such as UART, SPI, I2C, etc. Keywords: SPI, I2C, FPGA. 1. Introduction and synthesis of design and implementation on the FPGA platform; Part 5 is the conclusion of the paper Serial * Peripheral Interface (SPI) is one of the and the research team's next development direction on most widely used interfaces between microcontrollers the design of SPI to I2C protocol converter. and peripherals such as sensors, analog-to-digital converters (ADC), and digital-to-analog converters 2. Block Diagram Design (DAC), shift register or SRAM. Whereas Inter 2.1. Overview of the Converter Integrated Circuit (I2C) is a two-wire bus used to enable communication between two or more devices A protocol converter is a device that is used to on the same system. Let's assume an embedded system convert the standard communication (e.g. SPI) of one having only the SPI communication standard has to device to a suitable communication (e.g. I2C) with interface with peripherals that only use the I2C another device to have the ability to transmit data communication standard, next, by using design flow of between two communication standards. Fig. 1 shows ASIC (Application-Specific Integrated Circuit) and the block diagram of the system SPI to I2C protocol FPGA (Field-Programmable Gate Array) converter. technologies, a SPI to I2C communication converter is SS_N AD/DA LCD Driver created. Previously published researches such as Converter Design of SPI to I2C Bridge for High Speed Data SCLK SCL Interfacing in Digital System [1] and FPGA SPI2I2C SPI Master Implementation of Serial Protocol using SPI and I2C Bridge I2C Slave Controller Controller [2] have some limitations such as: Cannot transmit MOSI Controller SDA C Slave Interface C Master Interface 2 SPI Slave Interface I 2 SPI Master Interface data correctly if SPI device and I2C device operate in I MISO Serial LED Temperature different frequency domains; can’t use bus to EEPROMs Controller Sensors communicate with the system (APB, AHB, ); only can works with an initial pre configuration; the maximum Fig. 1. Connecting an SPI to I2C converter in a system. transfer rate of the I2C interface is only 3.4 Mbit/s. Therefore, the research team proposed to design an SPI 2.2. Serial Peripheral Interface to I2C protocol converter based on ASIC technology SPI is a synchronous serial communication and deployed it on the FPGA platform to solve these protocol that is commonly used at short distances, above problems. The structure of the paper is mostly in embedded systems between microprocessors organized as follows: In part 2, the block diagram or microcontrollers and peripherals like sensors, ADC, design of the SPI to I2C communication converter will DAC, SRAM, and so on. SPI devices communicate in be presented; Part 3 and part 4 bring up with testing ISSN: 2734-9373 Received: December 03, 2020; accepted: January 26, 2021 19
2. JST: Smart Systems and Devices Volume 31, Issue 2, September 2021, 019-026 the duplex-mode with only one single master device interrupt pins to respond to the current state of the and many slave devices. During communication, the circuit. Fig. 4 shows the general block diagram of the master can only pick a slave-based device by dragging SPI to I2C converter. the device's Slave Select (SS N) signal pin to a low level[3]. Fig. 2 illustrates SPI communication. SPI SS_N SS_N SPI Master Slave 2.3. Inter Integration Circuit SCLK SCLK Nowadays, in the communication protocols MOSI MOSI operating with low frequency, I2C (Inter Integrated Circuit) protocol is very suitable for communication MISO MISO between integrated circuits, slow communication with peripheral devices. Fig. 3 shows a transaction of the Fig. 2. SPI Interface I2C interface standard. For operation mode with 7-bit slave address, the master device will send a start condition, followed immediately by the 7-bit slave address which it wants to communicate with and finally a bit representing a write or read from the slave (bit 0 is written and bit 1 is read). If the slave exists on the bus, the slave will respond with the ACK bit (low-level to confirm) for its address. After that, the master will then be in read mode or write mode based on the previously sent written bit or read a bit [4]. The address and data bytes Fig. 3. A transaction of a standard I2C interface. are sent with the MSB bit first. Starting conditions occur when the SDA pulls from high-level to low- Rx_Data Config level when the SCL is high and stopping condition is rx_fifo_async_ff spi_slave SPI represented by the SDA transition from low-level to Req Rx_Data high-level when the SCL is high. Status Rx_data Rx FIFO Status Rx_cmd 2.4. Block Diagram APB Status Some previous architecture was given as follows: spi2i2c_reg_blk spi_to_i2_bridge_ctrl The SPI to I2C converter will contain a SPI interface INTR Status as the slave and a I2C interface as the master. All Tx FIFO Status request signals will be generated by the SPI master Control Tx_Data Req controller block. When an external SPI master wants Config to read or write data to an I2C slave peripheral, it sends tx_fifo_async_ff i2c_master I2C Tx_data a read command or write command and the Status corresponding address of the I2C slave through the internal SPI slave inside the converter. Thereon, the Fig. 4. Block diagram of SPI to I2C converter. SPI slave will then send commands, address, and data (in case of writing) to the I2C master, and the internal The blocks in Fig. 4 are shown and have the state machine will perform the necessary data following meanings: (1) spi2i2c_reg_blk: Is the block conversion. used to configure input values and store information about the active state of the converter; (2) spi_slave: Is These designs will only accommodate data a block designed to be equivalent as a simple SPI transmission with a clock domain, from there device. This block implements the SPI interface with proposing two more FIFO buffers (First in, first out) the external SPI master; (3) i2c_master: Is a block called TX FIFO (receiving data from the SPI-bus side) designed to be equivalent as a simple SPI device. This and RX FIFO (receiving data from the I2C-bus side) block implements I2C interface for data transmission for the purpose of storing pending data. Next, in order I2C slave devices; (4) spi_to_i2c_bridge_ctrl: Is the to communicate with the CPU and the user can main processing block of the converter. This block configure the converter, it is proposed to design a controls the transmission and reception of data from register block that is used to configure input values and two SPI slave block and I2C master block; (5) store input signal information. Output of the circuit. tx_fifo_async_ff: Is an asynchronous buffer, which This work is done through an advanced peripheral means that the write and read times on the watch may communication standard APB (Advanced Peripheral vary, and thus is commonly employed as a buffer data Bus) used to communicate with peripherals that do not storage devices. This block retains data that has been require fast processing speed such as UART, SPI, I2C, transmitted from an external SPI master and is waiting etc. In addition, the converter will have additional to be processed before being delivered to the I2C-bus; 20
3. JST: Smart Systems and Devices Volume 31, Issue 2, September 2021, 019-026 (6) rx_fifo_async_ff: This block stores data with the order of bytes sent as follows: 1 byte of the transmitted from external I2C slave devices waiting to read command (0x02), 1 byte of data for the number be processed to send those data to the SPI-bus. of bytes that the SPI master wants to receive (maximum 256 bytes) and 1 byte of data for the 2.5. Operating Principle address of the I2C slave device. Fig. 7 shows the data In order for the SPI master to communicate with stream sent on the SPI-bus when the SPI master the I2C slave devices, the research team designed a set performs a read command (0x02). of commands that can be customized according to the Table 1. The commands the SPI master can send on the previous convention between the two sides of the SPI SPI-bus. master and the converter, and then send those commands on the SPI-bus. Most SPI devices currently No Command Description operate data within a transaction (i.e. every time SS_N is active) whose number of bits transmitted must be a 1 0x01 Write N bytes to device I2C multiple of 8 from which the total width of a transaction on the SPI-bus Designed so that the 2 0x02 Read N bytes from I2C device number of bits is divisible by 8, this converter has an instruction width of 1 byte so that the SPI master can 3 0x03 Read buffer command. transmit properly. The SPI master commands that can be transmitted on the SPI-bus are listed in Table 1. The following is the data frame for the commands in the SPI Master sends message table: 0x01 NUMBE R SLAVE ADDRESS DATA . . . DATA COMMAND OF BYTES + W BYTE 1 BYTE N 2.5.1. Data transfer to slave I2C peripheral device (0x01) SS_N When the SPI master pulls the SS_N signal pin a SCLK low level, the data received from the external SPI master (SCLK) clocked MOSI pin is processed by the MOSI number of bytes D[7:0] slave address A[7:1] 0 data byte 1 data byte N SPI slave block in the converter and then forwarded to the processing block to add the elements of the I2C Fig. 5. Data is transferred over the SPI-bus when a interface standard as the start bit, the address bits, the write signal is issued, (0x01). ACK bit (controlled by the I2C slave) and the stop bit. The SPI master will send a command to the converter 2 Data transfer on the I C-bus in the following order of bytes: 1 byte of writting DATA DATA S SLAVE ADDRESS R/W A A . . . A/NA P/Sr instruction (0x01), 1 byte of data for the number of BYTE 1 BYTE N bytes that the SPI master wants to transmit (maximum P SDA 256 bytes), 1 byte of data for the address of the I2C Sr SCL 1 2 7 8 9 1 2 7 8 9 slave and finally the data transmitted to those I2C ACK A/NA devices. The data stream sent on the SPI-bus when the from master to slave A = acknowledge (SDA LOW) NA = not acknowledge (SDA HIGH) write command (0x01) is executed is shown as shown S = START condition P = STOP condition in Fig. 5. slave to master Sr = repeat start conditon The data after being filtered by the SPI slave Fig. 6. Data is transferred across the I2C-bus when the block continues to be processed by the processor block SPI master issues a write signal, (0x01). (spi_to_i2c_bridge_ctrl) and sent to the I2C master block for transmission to the I2C slave devices. Fig. 6 shows the data stream sent on the I2C-bus when the SPI Master sends message SPI master executes a write command (0x01). 0x02 NUMBE R SLAVE ADDRESS COMMAND OF BYTES + W 2.5.2. Receive data from slave I2C peripheral device The data received from the I2C slave devices are SS_N processed by the internal I2C master block by removing the I2C interface standard bits which are the SCLK start bit, the address bits, the ACK bit and the stop bit. MOSI number of bytes D[7:0] slave address A[7:1] 1 The received data is stored in the RX FIFO memory and will not be returned to the external SPI master Fig. 7. The data stream sent on the SPI-bus when the without executing the buffer read (0x03) instruction SPI master performs a read command (0x02). described in the next section. To receive data the SPI master will send a command to the I2C slave device 21
4. JST: Smart Systems and Devices Volume 31, Issue 2, September 2021, 019-026 2 Data transfer on the I C-bus DATA DATA S SLAVE ADDRESS R/W A A . . . NA P/Sr BYTE 1 BYTE N ss_n P sclk SDA Sr mosi don’t care SCL 1 2 7 8 9 1 2 7 8 9 ACK ACK valid_data from master to slave A = acknowledge (SDA LOW) miso NA = not acknowledge (SDA HIGH) S = START condition P = STOP condition slave to master Sr = repeat start conditon Fig. 8. The data stream sent on the I2C-bus when the Fig. 10. The data takes effect when the SPI master SPI master performs a read command (0x02). reads the buffer, SPI-bus data 0x03 DATA . . . DATA TOP Test COMMAND BYTE 1 BYTE N Environment Scoreboard Sequence from master to slave Monitor Sequencer DUT Driver slave to master Fig. 9. The data stream sent on the SPI-bus when the Fig. 11. Basic structure of UVM environment. SPI master performs a buffer read (0x03). The data after being filtered by the SPI slave Circuit) technology, before the product is packaged, it block is further processed by the processing block is critical to test the design. Building a verification (spi_to_i2c_bridge_ctrl) and sent to the I2C master environment has become an essential phase in the block for transmission to the I2C slave devices and product design process that cannot be overlooked in then receiving the returned data. Fig. 8 shows the data order to ensure that a product works properly under stream sent on the I2C-bus when the SPI master real-world settings. The UVM (Universal Verification performs a read (0x02). Methodology) library and QuestaSim software for design verification are two of the most successful 2.5.3. Read buffer verification approaches for ASIC-based designs [5]. After the SPI master executes a buffer read 3.1.1. Introduction to UVM library (0x03) command from the RX FIFO buffer, the data being stored in the buffer will be returned to the SPI UVM (Universal Verification Methodology) is a master via the MISO signal pin. Fig. 9 shows the data method of simulating hardware designs. The UVM stream sent on the SPI-bus when the SPI master library is a collection of classes and methods built on performs a buffer read (0x03). the System Verilog language. UVM was built with the goal of creating a common simulation method for the Because the speed of operation of the SPI and IC industry. Simulation testing is a very time- I2C communication protocols differs, data received consuming process. In particular, the time spent from the I2C device can be delivered at any moment building and editing the simulation environment is because the SS_N pin is pulled to a low level and the quite large. Without a common methodology, a SPI master cannot identify when the data takes effect, simulation environment will be difficult to reuse, Read buffer command (0x03) is created. As a result, extend and understand by many different engineers, the buffer reading command was designed to address organizations or companies. this issue. The data in effect when the SPI Master executes the buffer reading instruction is shown in The basic structure of a UVM environment Fig. 10. consisting of blocks is shown in Fig. 11. The blocks in Fig. 11 are described as follows: (1) Top is the element 3. Design Verification and Synthesis. that contains the entire test environment, including the 3.1. Design Testing. DUT; (2) Test is the top layer containing all UVM components; (3) DUT (Design Under Test) is the With an RTL (Register-Transfer Level) design design to be tested; (4) Environment is a grouping according to ASIC (Application-Specific Integrated 22
5. JST: Smart Systems and Devices Volume 31, Issue 2, September 2021, 019-026 element of other UVM environmental components will automatically extract code coverage from the RTL such as Agent and Scoreboard; (5) Agent groups the code. components that test the connection to the - dti_spi2i2c_sva (100%): is the result of communication of the DUT. It can have many different checking the correctness of the functions and timing components, but usually has 3 main components: required in the design. Monitor is the component that monitors information and communication signals with the DUT, Sequencer - dti_cvg (100%): shows that all items in the test controls the transmission of transactions from plan for design features have been tested. sequences, and Driver receives transactions. From the sequences is to convert them in turn to the dti_top_tb corresponding values to drive the signals for environment communication with the DUT; (6) Scoreboard is the agent sequencer component that examines the desired behavior, sequence Driver activity or data of the DUT and (7) Sequence is the item object that generates transactions and provides them to the UVM Sequencer to deliver to the Driver. SPI_IF spi2i2c_intf SVA Checker DUT spi_master_model 3.1.2. Build testbench structure SPI_IF i2c_interface Fig. 12 shows the block structure of UVM for i2c_slave_model design testing. The UVM class library brings a lot of automation to the SystemVerilog hardware description Fig. 12. Testbench structure using UVM to test the language such as sequencing and data automation design. features (packing, copying, comparing), etc. After building the structure testbench as shown in Fig. 11, perform design testing on QuestaSim software. Imagine that when a transaction (0x01) is executed, the data flow sent via the SPI-bus consists of the following 24 bits of commands: Write 0x01 with 8 bits of commands, 8 bits of transferred bytes, and 8 bits of I2C address. The SPI master will then send the actual Fig. 13. Simulation results of the converter on the SPI data on the I2C bus (in this example is 4 bytes of data). data input. On the SPI-bus, the operating frequency is 10 MHz, and I2C is in Fast-mode Plus (1 MHz). With the above operating frequency, the minimum required depth of TX FIFO is 10. Fig. 13 shows the design simulation results on the SPI-bus data input side. After receiving the input data from the SPI with the request to perform data transmission to the I2C slave device, the I2C interface of the converter will have the waveform shown in Fig. 14. Fig. 14. Simulation results of data transmission on The results after simulation are shown in Fig. 13 I2C-bus. and Fig. 14, when directly observed, it can be seen that the results are correct compared to the requirements set forth. But for the convenience of design testing, QuestaSim software with the use of the UVM library will generate a report, helping the designer to determine the correct operation and coverage of the design, thereby can create input plans and goals for parts of the design. The results when running the test cases will be saved by UVM and extracted to a coverage report generated on Questa software with the results as shown in Fig. 15. The important information of the coverage report includes: - dti_spi_to_i2c_top (87.83%): is the coverage result of code RTL coverage. It measures how much of the RTL code has been executed through all the test Fig. 15. Coverage report of the design on QuestaSim cases. This includes implementing design blocks, line software. numbers, conditions, FSM, toggles, and paths. UVM 23
6. JST: Smart Systems and Devices Volume 31, Issue 2, September 2021, 019-026 Each verified design requires coverage metrics to (positive), which means the design can work with the gauge performance and help determine when the original specified frequency of 150 MHz. design is good enough to stop. In this report the Startpoint:dti_spi2i2c_reg_blk/rb_regs/iscl_scl_low_cnt_reg[0](rising edge-triggered flip-flop clocked by pclk) dti_tb_top information reaches 92.39% indicating that Endpoint: dti_spi_to_i2c/dti_i2c_core/i2c_master_ctrl_inst/master_i2c_bit_cnt_inst design testing can be stopped to make the move to the /count_reg_reg[2](rising edge-triggered flip-flop clocked by clk) Path Group: clk next steps of the ASIC design flow. Path Type: max clock clk (rise edge) 45.00000 45.00000 clock network delay (ideal) 0.00000 45.00000 3.2. Design Synthesis clock uncertainty 3.00000 42.00000 dti_spi_to_i2c/dti_i2c_core/i2c_master_ctrl_inst/master_i2c_bit_cnt_inst /count_reg_reg[2]/CK (dti_ffqa01x1) Advanced techniques are used for ASIC chip 0.00000 42.00000 r library setup time 0.15634 41.84366 synthesis, physics synthesis, static timing testing and data required time 41.84366 slack(MET) 0.00030 analysis, optimization, dynamic simulation, formal normalization delay 5.00000 verification, DFT scan insertion, link to layout, normalized slack 0.00006 physical synthesis and static timing analysis using the 4. Design Implementation on FPGA Design Compiler tool of Synopsys [6]. Configure the software with an operating frequency of 150 MHz with 4.1. Deployment Block Diagram on Xilinx FPGA optimal options for timing, area and power. To be able Platform to synthesize, in addition to the RTL design, a library The I2C and I2S interfaces are designed to of standard cell is required, the library used for control the on-board audio codec to output audio synthesis in this design is a standard cell library with signals under this article, which is built on the Xilinx 40 nm technology, -40 oC operating temperature FPGA platform. Before being transferred to the codec, (which is the condition where standard cells work the audio data is stored in the FPGA's internal RAM block. worst) and the voltage used is 0.99 V. The important The SPI2I2C controller is the decoder configured via results are area (area) and time (timing) in the design the I2C interface. Digital audio data can be sent across synthesis are shown as follows: the DAC interface of the codec using the I2S controller 3.2.1 Area once it is configured and ready. Thereafter, the digital audio data is fed through the WM8731 Audio Codec Number of ports: 108 Number of nets: 6040 for conversion to analog signals and output to Number of cells: 5957 Number of combinational cells: 4394 multimedia devices [7]. The block diagram based on Number of sequential cells: 1563 Number of macros/black boxes: 0 the Xilinx FPGA platform is shown in Fig. 16. Number of buf/inv: 999 Number of references: 67 Combinational area: 5096.587949 In order for the implementation to be designed on Buf/Inv area: 587.608000 Noncombinational area: 6409.591938 FPGA, the selected FPGA platform should have at Macro/Black Box area: 0.000000 Net Interconnect area: undefined (No wire load specified) least the following parameters: (1) System frequency: Total cell area: 11506.179887 200 MHz; (2) controllers: I2C, I2S; (3) Support APB Area results including ports, nets, cells, Interface; (4) Software design support. From there, combined, non-combined and total area reports are using the Xilinx Kintex Ultra-Scale FPGA platform is shown in the report. The important information shown able to meet the listed requirements and is suitable for in the area report is that the number of combinational deploying IPs of great complexity. cells is 4394, the number of sequential cells is 1563, and the total design area is 11506.179887 (µm2). SPI Master Processor 3.2.2. Timing Controller AXI APB SPI I2C Slack is a type of timing in the Static Timing Clock APB SPI2I2C Analysis of techniques for testing designs in terms of APB BRIDGE WM8731 Clock Divider Controller Audio Codec time. Slack includes setup slack and hold slack, Reset_n defined as the difference between the actual or APB I2S achieved time and the desired time for a timing path. Block RAM I2S Controller Slack timing path helps designers determine their FPGA Platform design can work with the required frequency or not. Below is a part of the report with the part cited as the Fig. 16. Deployment block diagram on Xilinx FPGA path with the lowest slack line. The important platform. information shown in the report is the slack parameter, 4.2. Work if the result of an aggregate is the result of slack (MET) The BRAM block carries the original data in the means that the value of slack is a non-negative value coe file format. Furthermore, using the I2C interface and the design can work with the frequency generated by the SPI2I2C converter to configure the considered, otherwise slack (VIOLATED) means that internal registers of the WM8731 Audio Codec, assign the design value of slack is a negative value and the the registers inside the IPs to SPI Master, SPI2I2C, and design cannot work with the frequency considered. In I2S. After configuring the IP register configuration, this report, the slack (MET) is equal to 0.00030 ns allow the I2S SCK clock to synchronize data between 24
7. JST: Smart Systems and Devices Volume 31, Issue 2, September 2021, 019-026 I2S and WM8731. The values inside the BRAM are + + + + read out and recorded in the FIFO memory, and the | Ref Name | Used | Functional Category | + + + + step was repeated until the BRAM signals the data to | FDRE | 800 | Register | be empty. The operational flow of the design | LUT6 | 744 | CLB | implemented on the Xilinx FPGA can be seen in | FDCE | 741 | Register | | LUT4 | 212 | CLB | Fig. 17. | LUT2 | 202 | CLB | | LUT5 | 167 | CLB | | LUT3 | 142 | CLB | Initialize audio data | MUXF7 | 100 | CLB | Read data from BRAM and False write to TX FIFO | INBUF | 52 | I/O | TX FIFO True | IBUFCTRL | 52 | Others | Configure SPI2I2C Controller Transmit data Empty? | OBUF | 49 | I/O | Configure I2S Controller | FDPE | 29 | Register | False Bram Empty? | CARRY8 | 14 | CLB | Configue WM8731 Codec | LUT1 | 11 | CLB | True | MUXF8 | 9 | CLB | Disable clock and FIFO Enable I2S Master clock | OBUFT | 2 | I/O | FINISH | BUFGCE | 2 | Clock | + + + + Fig. 17. The operational flow of the design 5. Discussion Results. implemented on the Xilinx FPGA. Table 2 compares the design features of the 4.3. Synthesized Results on FPGA. converter by the design team with previously The following synthesis results were generated published papers such as Design of SPI to I2C Bridge by the converter using Xilinx Vivado 2018.1 software for High-Speed Data Interfacing in Digital System of with a configured operating frequency of 150 Mhz. IJARCCE, FPGA Implementation of Serial Protocol using SPI and I2C of IJEEE and industrial products of 4.3.1. CLB Logic other companies such as Silicon Labs' CP2120 [8] or Club Logic is a critical component of FPGA NXP's SC18IS600 [9]. The current design of the technology. Reconfigurable logic gates may be created research team solved the problems posed in the using logic blocks. The most typical FPGA introduction. Table 2 shows that SPI mode can work architecture is logic blocks, which are commonly with all modes of SPI protocol, so it can communicate arranged in an array. I/Os (to communicate with with all systems which have SPI bus. The design uses external signals) and routing channels are required by the APB peripheral communication bus with a faster logic blocks (to connect logic blocks). A logic block is register configuration speed than using the SPI bus made up of many logic cells (called ALM, LE, Slice, directly for configuration like Silicon Labs’s product. ). One cell consists of a 4-input LUT, a Full Adder, Today, technology products are increasingly and a D-type flip-flop. Below is the result of the developed, the speed of system communication must synthesized logic CLB. The results show that the also increase to meet the needs. Therefore, the research number of CLB LUTs used accounted for only 0.24%, team has considered improving the speed of SPI and CLB Register accounted for 0.15%, which means that I2C interface standards in the design. the design takes up very little resources of the FPGA. Table 2. Compare and contrast the design aspects of + + + + + + | Site Type | Used | Fixed | Available | Util% | various converters. + + + + + + | CLB LUTs* | 1264 | 0 | 537600 | 0.24 | Silicon dti_spi2i IJARCC IJERT NXP [9] | LUT as Logic | 1264 | 0 | 537600 | 0.24 | Features Labs [8] (SC18IS6 2c (Our E [1] [2] | LUT as Memory | 0 | 0 | 76800 | 0.00 | (CP2120) 00) Design) | CLB Registers | 1570 | 0 | 1075200 | 0.15 | Mode Not Not Mode 0, | Register as Flip Flop | 1570 | 0 | 1075200 | 0.15 | Mode 3 Mode 3 | Register as Latch | 0 | 0 | 1075200 | 0.00 | SPI mention. mention. 1, 2, 3 | CARRY8 | 14 | 0 | 67200 | 0.02 | SPI data | F7 Muxes | 100 | 0 | 268800 | 0.04 | transmis Not Not LSB or LSB or | F8 Muxes | 9 | 0 | 134400 | <0.01 | MSB sion mention. mention. MSB MSB | F9 Muxes | 0 | 0 | 67200 | 0.00 | direction + + + + + + Register Can’t Can’t Using Using Using configur configura configur SPI bus SPI bus APB bus 4.3.2. Primitives ation ble. able. SPI Not Not 1.2 25 A resource in an FPGA that is directly recognized 1 Mbit/s speed mention. mention. Mbit/s Mbit/s by the implementation software and typically I2C max 3.4 3.4 400 corresponds to a logical resource in a logic resource 400 kbit/s 5 Mbit/s (e.g. I/O pin, buffer, logic gate, or flip-flop). The report speed Mbit/s Mbit/s kbit/s 256 below shows the average number of Primitives used Buffer Not Not 256 bytes 96 bytes compared to a small IP core deployed on an FPGA. bytes 25
8. JST: Smart Systems and Devices Volume 31, Issue 2, September 2021, 019-026 The speed of the SPI interface is also References significantly improved from 1.2 Mbit/s up to 25 Mbit/s [1]. Sidra Anam and Vinod Kapse, Design of SPI to I2C by making this design works well with most of the bridge for high speed data interfacing in digital system, systems which using the SPI interface standard International Journal of Advanced Research in available on the market. In addition, the speed of the Computer and Communication Engineering, Vol. 5, I2C interface is also improved to a maximum of Issue 4, April 2016. 5 Mbit/s. [2]. Saniya Farheen and Dr Baswaraj Gadgay, FPGA Because of the speed disparity between SPI and implementation of serial protocol using SPI and I2C, I2C, a buffer is required to hold data received from the International Journal of Ethics in Engineering & two interfaces. The buffer's breadth grows in Management Education (IJEEE), Volume 2, Issue 6, proportion to the difference between the two values. June 2015. This design solves the problem of the performance gap [3]. Sanjeeb Mishra and Vijayakrishnan Rousseau, System between the two communication protocols being too on chip interfaces for low power design, Elsevier Inc, big by using a 256-byte buffer, however, this increases 2016, pp. 239-243. the hardware cost of the design. 6. Conclusion [4]. Sanjeeb Mishra and Vijayakrishnan Rousseau, System The converter designed by the research team can on chip interfaces for low power design, Elsevier Inc, work with all the features proposed by the founders of 2016, pp. 243-247. these two communication standards that some other [5]. Uvm Cookbook Complete Verification Academy, 1rd, industrial companies do not have. Menter Graphics, 2017, pp. 1-4. The protocol converter design is proposed to be [6]. S. Gayathri and T. C. Taranath, RTL synthesis of case implemented in both ASIC and FPGA technologies, study using design compiler, in Proc. 2017 according to the study. The protocol converter has International Conference on Electrical, Electronics, Communication, Computer, and Optimization more features than the previous mentioned designs in Techniques (ICEECCOT), 2017, pp. 1-7, terms of design. For example, to compensate for the speed differential between the two communication standards, a set of two FIFO buffers has been [7]. Peter Athanas, Dionisios Pnevmatikatos and Nicolas incorporated to the architecture. Additionally, the SPI Sklavos, Embedded systems design with FPGAs, and I2C bus speeds have been enhanced (25 MHz SPI- Springer, 2015, pp. 1-4. bus and 5 MHz I2C-bus). Furthermore, the design is [8]. SPI To I2c Bridge And Gpio Port Expander, 1rd, capable of operating at a high frequency of up to Silicon Labs, 2015. 150 MHz. [9]. SPI to I2C-bus Interface, 8rd, NXP Semiconductors, 2019. 26