Digital Design with the Verilog HDL - Chapter 1: Introduction to Verilog

Nội dung text: Digital Design with the Verilog HDL - Chapter 1: Introduction to Verilog

1. Digital Design with the Verilog HDL Chapter 1: Introduction to Verilog Dr. Phạm Quốc Cường Adapted from Prof. Mike Schulte’s slides (schulte@engr.wisc.edu) Computer Engineering – CSE – HCMUT 1
2. Overview of HDLs • Hardware description languages (HDLs) – Are computer-based hardware description languages – Allow modeling and simulating the functional behavior and timing of digital hardware – Synthesis tools take an HDL description and generate a technology-specific netlist • Two main HDLs used by industry – Verilog HDL (C-based, industry-driven) – VHSIC HDL or VHDL (Ada-based, defense/industry/university-driven). 2
3. Synthesis of HDLs • Takes a description of what a circuit DOES • Creates the hardware to DO it • HDLs may LOOK like software, but they’re not! – NOT a program – Doesn’t “run” on anything • Though we do simulate them on computers – Don’t confuse them! • Also use HDLs to test the hardware you create – This is more like software 3
4. Describing Hardware! • All hardware created during if (a) f = c & d; synthesis else if (b) f = d; – Even if a is true, still else f = d & e; computing d&e • Learn to understand how descriptions translated to c hardware f d e b a 4
5. Why Use an HDL? • More and more transistors can fit on a chip – Allows larger designs! – Work at transistor/gate level for large designs: hard – Many designs need to go to production quickly • Abstract large hardware designs! – Describe what you need the hardware to do – Tools then design the hardware for you 5
6. Why Use an HDL? • Simplified & faster design process • Explore larger solution space – Smaller, faster, lower power – Throughput vs. latency – Examine more design tradeoffs • Lessen the time spent debugging the design – Design errors still possible, but in fewer places – Generally easier to find and fix • Can reuse design to target different technologies – Don’t manually change all transistors for rule change 6
7. Other Important HDL Features • Are highly portable (text) • Are self-documenting (when commented well) • Describe multiple levels of abstraction • Represent parallelism • Provides many descriptive styles – Structural – Register Transfer Level (RTL) – Behavioral • Serve as input for synthesis tools 7
8. Verilog • In this class, we will use the Verilog HDL – Used in academia and industry • VHDL is another common HDL – Also used by both academia and industry • Many principles we will discuss apply to any HDL • Once you can “think hardware”, you should be able to use any HDL fairly quickly 8
9. Verilog Module • In Verilog, a circuit is a module. A[1:0] 2 module decoder_2_to_4 (A, D) ; Decoder 2-to-4 input [1:0] A ; output [3:0] D ; 4 assign D = (A == 2'b00) ? 4'b0001 : D[3:0] (A == 2'b01) ? 4'b0010 : (A == 2'b10) ? 4'b0100 : (A == 2'b11) ? 4'b1000 ; endmodule 9
10. Verilog Module A[1:0] module name ports names of module 2 module decoder_2_to_4 (A, D) ; Decoder 2-to-4 port input [1:0] A ; port types output [3:0] D ; sizes 4 assign D = (A == 2'b00) ? 4'b0001 : D[3:0] (A == 2'b01) ? 4'b0010 : (A == 2'b10) ? 4'b0100 : (A == 2'b11) ? 4'b1000 ; module contents endmodule keywords underlined 10
11. Declaring A Module • Can’t use keywords as module/port/signal names – Choose a descriptive module name • Indicate the ports (connectivity) • Declare the signals connected to the ports – Choose descriptive signal names • Declare any internal signals • Write the internals of the module (functionality) 11
12. Declaring Ports • A signal is attached to every port • Declare type of port – input – output – inout (bidirectional) • Scalar (single bit) - don’t specify a size – input cin; • Vector (multiple bits) - specify size using range – Range is MSB to LSB (left to right) – Don’t have to include zero if you don’t want to (D[2:1]) – output [7:0 ] OUT; – input [1:0] IN; 12
13. Module Styles • Modules can be specified different ways – Structural – connect primitives and modules – RTL – use continuous assignments – Behavioral – use initial and always blocks • A single module can use more than one method! • What are the differences? 13
14. Structural • A schematic in text form • Build up a circuit from gates/flip-flops – Gates are primitives (part of the language) – Flip-flops themselves described behaviorally • Structural design – Create module interface – Instantiate the gates in the circuit – Declare the internal wires needed to connect gates – Put the names of the wires in the correct port locations of the gates • For primitives, outputs always come first 14
15. Structural Example module majority (major, V1, V2, V3) ; output major ; input V1, V2, V3 ; V1 N1 V2 A0 wire N1, N2, N3; V2 N2 and A0 (N1, V1, V2), A1 Or0 major A1 (N2, V2, V3), V3 A2 (N3, V3, V1); V3 N3 or Or0 (major, N1, N2, N3); A2 V1 endmodule majority 15
16. RTL Example module majority (major, V1, V2, V3) ; output major ; input V1, V2, V3 ; V1 assign major = V1 & V2 | V2 & V3 V2 majority major | V1 & V3; endmodule V3 16
17. Behavioral Example module majority (major, V1, V2, V3) ; output reg major ; input V1, V2, V3 ; always @(V1, V2, V3) begin if (V1 && V2 || V2 && V3 V1 || V1 && V3) major = 1; V2 majority major else major = 0; end V3 endmodule 17
18. Adder Example 18
19. Full Adder: Structural module half_add (X, Y, S, C); module full_add (A, B, CI, S, CO) ; input X, Y ; input A, B, CI ; output S, C ; output S, CO ; xor SUM (S, X, Y); wire S1, C1, C2; and CARRY (C, X, Y); // build full adder from 2 half-adders endmodule half_add PARTSUM (A, B, S1, C1); hafl_add SUM (S1, CI, S, C2); // and an OR gate for the carry or CARRY (CO, C2, C1); endmodule 19
20. Full Adder: RTL/Dataflow module fa_rtl (A, B, CI, S, CO) ; input A, B, CI ; output S, CO ; // use continuous assignments assign S = A ^ B ^ CI; assign C0 = (A & B) | (A & CI) | (B & CI); endmodule 20
21. Full Adder: Behavioral • Circuit “reacts” to given events (for simulation) – Actually list of signal changes that affect output module fa_bhv (A, B, CI, S, CO) ; input A, B, CI; output S, CO; reg S, CO; // explained in later lecture – “holds” values // use procedural assignments always@(A or B or CI) begin S = A ^ B ^ CI; CO = (A & B) | (A & CI) | (B & CI); end endmodule 21
22. Full Adder: Behavioral • IN SIMULATION – When A, B, or C change, S and CO are recalculated • IN REALITY – Combinational logic – no “waiting” for the trigger – Constantly computing - think transistors and gates! – Same hardware created for this and RTL example A S always@(A or B or CI) B begin CI S = A ^ B ^ CI; majority CO CO = (A & B) | (A & CI) | (B & CI); end fa_bhv 22
23. Structural Basics: Primitives • Build design up from the gate/flip-flop/latch level – Flip-flops actually constructed using Behavioral • Verilog provides a set of gate primitives – and, nand, or, nor, xor, xnor, not, buf, bufif1, etc. – Combinational building blocks for structural design – Known “behavior” – Cannot access “inside” description • Can also model at the transistor level – Most people don’t, we won’t 23
24. Primitives • No declarations - can only be instantiated • Output port appears before input ports • Optionally specify: instance name and/or delay (discuss delay later) and N25 (Z, A, B, C); // name specified and #10 (Z, A, B, X), (X, C, D, E); // delay specified, 2 gates and #10 N30 (Z, A, B); // name and delay specified 24
25. Verilog Primitives • 26 pre-defined primitives • Output is the first port n-output n-input output ending mark 3-states and buf nand (y, a, b, c); nand not input keyword name or bufif0 nor bufif1 xor notif0 nand N1(y, a, b, c); xnor notif1 instance name (optional) 25
26. Syntax For Structural Verilog • First declare the interface to the module – Module keyword, module name – Port names/types/sizes • Next, declare any internal wires using “wire” – wire [3:0] partialsum; • Then instantiate the primitives/submodules – Indicate which signal is on which port 26
27. Again: Structural Example module majority (major, V1, V2, V3) ; output major ; input V1, V2, V3 ; V1 N1 V2 A0 wire N1, N2, N3; V2 N2 and A0 (N1, V1, V2), A1 Or0 major A1 (N2, V2, V3), V3 A2 (N3, V3, V1); V3 N3 or Or0 (major, N1, N2, N3); A2 V1 endmodule majority 27
28. Example • Using the Verilog structural style, describe the following circuit 28
29. Example: Combinational Gray code S2’ = Rst S2 S0 + Rst S1 S0 S1’ = Rst S2 S0 + Rst S1 S0 S0’ = Rst S2 S1 + Rst S2 S1 29
30. Datatypes • Two categories – Nets – “Registers” • Only dealing with nets in structural Verilog • “Register” datatype doesn’t actually imply an actual register – Will discuss this when we discuss Behavioral Verilog 30
31. Net Types • wire: most common, establishes connections – Default value for all signals • tri: indicates will be output of a tri-state – Basically same as “wire” • supply0, supply1: ground & power connections – Can imply this by saying “0” or “1” instead – xor xorgate(out, a, 1’b1); • wand, wor, triand, trior, tri0, tri1, trireg – Perform some signal resolution or logical operation – Not used in this course 31
32. Structural Verilog: Connections • “Positional” or “Implicit” port connections – Used for primitives (first port is output, others inputs) – Can be okay in some situations • Designs with very few ports • Interchangeable input ports (and/or/xor gate inputs) – Gets confusing for large #s of ports • Can specify the connecting ports by name – Helps avoid “misconnections” – Don’t have to remember port order – Can be easier to read – . ( ) 32
33. Connections Examples • Variables – defined in upper level module – wire [3:2] X; wire W_n; wire [3:0] word; • By position – module dec_2_4_en (A, E_n, D); – dec_2_4_en DX (X[3:2], W_n, word); • By name – module dec_2_4_en (A, E_n, D); – dec_2_4_en DX (.E_n(W_n), .A(X[3:2]), .D(word)); • In both cases, A = X[3:2], E_n = W_n, D = word 33
34. Empty Port Connections • Example: module dec_2_4_en(A, E_n, D); – dec_2_4_en DX (X[3:2], , word); // E_n is high impedence (z) – dec_2_4_en DX (X[3:2], W_n , ); // Outputs D[3:0] unused. • General rules – Empty input ports => high impedance state (z) – Empty output ports => output not used • Specify all input ports anyway! – Usually don’t want z as input – Clearer to understand & find problems • Helps if no connection to name port, but leave empty: – dec_2_4_en DX(.A(X[3:2]), .E_n(W_n), .D()); 34
35. Hierarchy • Any Verilog design you do will be a module • This includes testbenches! • Interface (“black box” representation) – Module name, ports • Definition – Describe functionality of the block – Includes interface • Instantiation – Use the module inside another module 35
36. Hierarchy • Build up a module from smaller pieces – Primitives – Other modules (which may contain other modules) • Design: typically top-down • Verification: typically bottom-up Full Adder Hierarchy Add_full Add_half Add_half or xor and xor and 36
37. Add_half Module Add_half xor and module Add_half(c_out, sum, a, b); output sum, c_out; input a, b; xor sum_bit(sum, a, b); and carry_bit(c_out, a, b); endmodule 37
38. Add_full Module Add_full Add_half Add_half or module Add_full(c_out, sum, a, b, c_in) ; output sum, c_out; input a, b, c_in; wire w1, w2, w3; Add_half AH1(.sum(w1), .c_out(w2), .a(a), .b(b)); Add_half AH2(.sum(sum), .c_out(w3), .a(c_in), .b(w1)); or carry_bit(c_out, w2, w3); endmodule 38
39. Can Mix Styles In Hierarchy! module Add_half_bhv(c_out, sum, a, b); output reg sum, c_out; input a, b; always @(a, b) begin sum = a ^ b; c_out = a & b; end endmodule module Add_full_mix(c_out, sum, a, b, c_in) ; output sum, c_out; input a, b, c_in; wire w1, w2, w3; Add_half_bhv AH1(.sum(w1), .c_out(w2), .a(a), .b(b)); Add_half_bhv AH2(.sum(sum), .c_out(w3), .a(c_in), .b(w1)); assign c_out = w2 | w3; endmodule 39
40. Hierarchy And Scope • Parent cannot access “internal” signals of child • If you need a signal, must make a port! Example: module add8bit(cout, sum, a, b); Detecting overflow output [7:0] sum; output cout; Overflow = input [7:0] a, b; cout XOR cout6 wire cout0, cout1, cout6; FA A0(cout0, sum[0], a[0], b[0], 1’b0); Must output FA A1(cout1, sum[1], a[1], b[1], cout0); overflow or cout6! FA A7(cout, sum[7], a[7], b[7], cout6); endmodule 40
41. Example: Gray code counter Implement: module gray_counter(out, clk, rst); //3 bit Use: module dff(clk, d, q, rst); module comb_gray_code(ns, rst, out); primitives clk ns out Counter Gray 0ð7 code rst 41
42. Implement the Counter module • Assume that the schematic of the counter module is as following 42
43. Interface: Gray code counter module gray_counter(out, clk, rst); output [2:0] out; input clk, rst; wire [2:0] ns; endmodule 43
44. Hierarchy And Source Code • Can have all modules in a single file – Module order doesn’t matter! – Good for small designs – Not so good for bigger ones – Not so good for module reuse (cut & paste) • Can break up modules into multiple files – Helps with organization – Lets you find a specific module easily – Great for module reuse (add file to project) 44