Digital Design with the Verilog HDL - Chapter 4: RTL Model

Nội dung text: Digital Design with the Verilog HDL - Chapter 4: RTL Model

1. Digital Design with the Verilog HDL Chapter 4: RTL Model Dr. Phạm Quốc Cường Use some Prof. Mike Schulte’s slides (schulte@engr.wisc.edu) Computer Engineering – CSE – HCMUT 1
2. RTL Verilog • Higher-level of description than structural – Don’t always need to specify each individual gate – Can take advantage of operators • More hardware-explicit than behavioral – Doesn’t look as much like software – Frequently easier to understand what’s happening • Very easy to synthesize – Supported by even primitive synthesizers 2
3. Continuous Assignment • Implies structural hardware assign = ; • Example wire out, a, b; assign out = a & b; • If RHS result changes, LHS is updated with new value – Constantly operating (“continuous”!) – It’s hardware! • Used to model combinational logic and latches 3
4. Full Adder: RTL/Dataflow • Example from Lecture 02 A S B CI module fa_rtl (A, B, CI, S, CO) ; input A, B, CI ; CO output S, CO ; // use continuous assignments fa_rtl assign S = A ^ B ^ CI; assign C0 = (A & B) | (A & CI) | (B & CI); endmodule 4
5. RTL And Structural Combined! Add_full Add_half Add_half or module Add_half(sum, cout, a, b); module Add_full(c_out, sum, a, b, c_in) ; output sum, cout; output sum, c_out; input a, b; input a, b, c_in; assign sum = a ^ b; wire psum, c1, c2; assign cout = a & b; endmodule Add_half AH1(partsum, c1, a, b); Add_half AH2(sum, c2, psum, c_in); assign c_out = c1 | c2; endmodule 5
6. Continuous Assignment LHS • Can assign values to: – Scalar nets – Vector nets – Single bits of vector nets – Part-selects of vector nets – Concatenation of any of the above • Examples: assign out[7:4] = a[3:0] | b[7:4]; assign val[3] = c & d; assign {a, b} = stimulus[15:0]; 6
7. Continuous Assignment RHS • Use operators: – Arithmetic, Logical, Relational, Equality, Bitwise, Reduction, Shift, Concatenation, Replication, Conditional – Same set as used in Behavioral Verilog • Can also be a pass-through! assign a = stimulus[16:9]; assign b = stimulus[8:1]; assign cin = stimulus[0]; – Note: “aliasing” is only in one direction • Cannot give ‘a’ a new value elsewhere to set stimulus[16:9]! 7
8. Implicit Continuous Assignments • Can create an implicit continuous assign • Goes in the wire declaration wire [3:0] sum = a + b; • Can be a useful shortcut to make code succinct, but doesn’t allow fancy LHS combos assign {cout, sum} = a + b + cin; • Personal choice – You are welcome to use it when appropriate 8
9. Implicit Wire Declaration • Can create an implicit wire • When wire is used but not declared, it is implied module majority(output out, input a, b, c); assign part1 = a & b; assign part2 = a & c; assign part3 = b & c; assign out = part1 | part2 | part3; endmodule • Lazy! Don’t do it! – Use explicit declarations – To design well, need to be “in tune” with design! 9
10. Verilog Operators Operator Name Group Operator Name Group [ ] Select > Shift right ! Negation (inverse) Logical > Greater ~ Negation (not) Bit-wise >= Greater or equal Relational & Reduction AND < Less | Reduction OR <= Less or equal ~& Reduction NAND Reduction == Equal (logic) ~| Reduction NOR != Not equal (logic) ^ Reduction XOR Equal ~^ or ^~ Reduction XNOR === Equal (case) !== Not equal (case) + Positive (unary) Arithmetic – Negative (unary) & bit-wise AND {} Concatenation Concat. ^ bit-wise XOR Bit-wise {{}} Replication Repl. ^~ or ~^ bit-wise XNOR * Multiplication | bit-wise OR / Division && logical AND % Modulus Arithmetic Logic || logical OR + Addition – Subtraction ?: Conditional Conditional 10
11. Arithmetic Operators (+, -, *, /, %) A  C B • If any bit in the operands is x or z, the result will be x • The result’s size – Mul: sum of both operands – Others: size of the bigger operand A = 4’b0010 (2) C = 4’b1101 (13) – B = 4’b0101 (5) 11
12. Relational Operators ( , =) A  True/False (1/0) B A = 52 A = 3’b001  x False (0) B = 5’b01011 12
13. Equality Operators (==, ===, !=, !===) • Logical comparison (== and !=) – The x and z values are processed as in Relative operators – The result may be x • Case comparison (=== and !==) – Bitwise compare – x === x, z === z, x !== z – The result is always 0 or 1 • If two operands are not the same size, 0(s) will be inserted into MSB bits of the smaller operand Data = 4’b11x0; Addr = 4’b11x0; Data == Addr //x Data === Addr //1 13
14. Logical Operators (||, &&, !) • Vector with at least one bit 1 is 1 • If any bit in the operands is x or z, the result will be x ABus = 4’b0110; BBus = 4’b0100; ABus || BBus // 1 ABus && BBus // 1 !ABus // Similar to!BBus // 0 14
15. Bit-wise Operators (&, |, ~, ^, ^~) & (and) 0 1 x z | (or) 0 1 x z 0 0 0 0 0 0 0 1 x x 1 0 1 x x 1 1 1 1 1 x 0 x x x x x 1 x x z 0 x x x z x 1 x x ^ (xor) 0 1 x z ^~ (xnor) 0 1 x z 0 0 1 x x 0 1 0 x x 1 1 0 x x 1 0 1 x x x x x x x x x x x x z x x x x z x x x x ~ (not) 0 1 x z 1 0 x x 15
16. Reduction Operators x x f z f x & (and reduction): &bn-1bn-1 b0 0 & 0 1 1 1 1 & 1 ~& (nand reduction): ~&bn-1bn-1 b0 & ~ 0/1 | (or reduction): |bn-1bn-1 b0 0 1 | 1 0 0 0 0 | ~| (nor reduction): ~|bn-1bn-1 b0 | ~ 0/1 ^ (xor reduction): ^bn-1bn-1 b0 If count(bi = 1) mod 2 == 0, return 0; otherwise return 1 ~^/^~ (xnor reduction): ~^bn-1bn-1 b0 16
17. Shift Operators( >) A > B x z f z z z f z z z • Shift the left operand the number of times represented by the right operand bn bn-1 b2 b1 b0 – Shift left bn-1 bn-2 b1 b0 0 0 bn bn-1 b2 b1 b0 – Shift right 0 0 bn b3 b2 b1 reg [0:7] Qreg; Qreg = 4’b0111; Qreg >> 2 // is 8’b0000_0001 wire [0:3] DecoderOut = 4’d1 << Address[0:1]; 17
18. Conditional Operator Cond_expr ? Expr1 : Expr2 • If Cond_expr includes any x bit or z bit, the result will be a “bitwise operation” of Expr1 and Expr2 as no following: Cond_expr? – 0. 0 => 0 yes – 1 . 1 => 1 – otherwise x • Infinite nested conditional Expr2 operator Expr1 Wire [15:0]bus_a = drive_a ? data : 16’bz; /* drive_a = 1 data is copied to bus_a drive_a = 0 bus_a is high-Z drive_a = x bus_a is x */ 18
19. Concatenation and Replication Operators • Concatenation {expr1, expr2, , exprN} – Does not work with un-sized constants wire [7:0] Dbus; wire [11:0] Abus; assign Dbus[7:4] = {Dbus[0], Dbus[1], Dbus[2], Dbus[3]}; assign Dbus = {Dbus[3:0], Dbus[7:4]}; {Dbus, 5} // not allowed • Replication {rep_number {expr1, expr2, , exprN}} Abus = {3{4’b1011}}; // 12’b1011_1011_1011 {3{1’b1}} // 111 {3{Ack}} // {Ack, Ack, Ack} 19
20. Expression Bit Lengths Expression Bit length Commnets Unsized constant number Same as integer (32 bit) Sized constant number As given i j, where is: Max(L(i),L(j)) +, -, *, /, %, |, ^, ~^ i j, where is: 1 bit Operands are sized to ===, !==, ==, !=, &&, ||, >, >=, Max(L(i),L(j)) j, where is: 1 bit &, ~&, |, ~|, ^, ~^, ! i j, where is: L(i) >>, << 20
21. Example: adder4b module adder4b (sum, c_out, a, b, c_in); input [3:0] a, b; input c_in; output [3:0] sum; output c_out; assign {c_out, sum} = a + b + c_in; endmodule 4 a[3:0] 4 4 sum[3:0] b[3:0] adder4b c_out c_in 21
22. Example: Unsigned MAC Unit Design a multiply-accumulate (MAC) unit that computes Z[7:0] = A[3:0]*B[3:0] + C[7:0] It sets overflow to one, if the result cannot be represented using 8 bits. module mac(output [7:0] Z, output overflow, input [3:0] A, B, input [7:0] C); 22
23. Solution: Unsigned MAC Unit module mac(output [7:0] Z, output overflow, input [3:0] A, B, input [7:0] C); wire [8:0] P; assign P = A*B + C; assign Z = P[7:0]; assign overflow = P[8]; endmodule Alternative method: module mac(output [7:0] Z, output overflow, input [3:0] A, B, input [7:0] C); assign {overflow, Z} = A*B + C; endmodule 23
24. Example: Multiplexer module mux_8_to_1(output out, input in0, in1, in2, in3, in4, in5, in6, in7, input [2:0] sel); Use the conditional operator and a single continuous assignment statement 24
25. Solution: Multiplexer module mux_8_to_1(output out, input in0, in1, in2, in3, in4, in5, in6, in7, input [2:0] sel); assign output = endmodule 25
26. Latches 26
27. Latches • Continuous assignments with feedback module latch(output [7:0] q_out, input [7:0] data_in, enable); assign q_out = enable ? data_in : q_out; endmodule module latch_reset(output q_out, input data_in, enable, reset); assign q_out = reset ? 0 : (enable ? data_in : q_out); endmodule • How would we change these for 8-bit latches? • How would we make the enable active low? 27
28. Example: Rock-Paper-Scissors • module rps(win, player, p0guess, p1guess); • Assumptions: – Input: p0guess, p1guess = {0 for rock, 1 for paper, 2 for scissors} – Output: player is 0 if p0 wins, 1 if p1 wins, and don’t care if there is a tie – Output: win is 0 if there is a tie and 1 if a player wins • Reminders – Paper beats rock, scissors beats paper, rock beats scissors – Same values tie 28
29. Example: Rock-Paper-Scissors • Two possible approaches – Figure out the Boolean equations for win and player and implement these using continuous assignments • Use bitwise operators – Examine what the various items equal and do logical operations on these • Use equality and logical operators 29
30. Solution 1: Rock-Paper-Scissors module rps(win, player, p0guess, p1guess); input [1:0] p0guess, p1guess; output win, player; endmodule 30
31. Solution 2: Rock-Paper-Scissors module rps(win, player, p0guess, p1guess); input [1:0] p0guess, p1guess; output win, player; endmodule What is are the advantages of each approach? 31