Digital Design with the Verilog HDL - Chapter 5: Behavioral Model - Part 1

Nội dung text: Digital Design with the Verilog HDL - Chapter 5: Behavioral Model - Part 1

1. Digital Design with the Verilog HDL Chapter 5: Behavioral Model - part 1 Dr. Phạm Quốc Cường Use some Prof. Mike Schulte’s slides (schulte@engr.wisc.edu) Computer Engineering – CSE – HCMUT 1
2. Behavioral Verilog • Use procedural blocks: initial, always • These blocks contain series of statements – Abstract – works *somewhat* like software – Be careful to still remember it’s hardware! • Parallel operation across blocks – All blocks in a module operate simultaneously • Sequential or parallel operation within blocks – Depends on the way the block is written – Discuss this in a later lecture • LHS of assignments are variables (reg) 2
3. Types of Blocks • initial – Behavioral block operates ONCE – Starts at time 0 (beginning of operation) – Useful for testbenches – Can sometimes provide initialization of memories/FFs • Often better to use “reset” signal – Inappropriate for combinational logic – Usually cannot be synthesized • always – Behavioral block operates CONTINUOUSLY – Can use a trigger list to control operation; @(a, b, c) 3
4. initial vs. always reg [7:0] v1, v2, v3, v4; reg [7:0] v1, v2, v3, v4; initial begin always begin v1 = 1; v1 = 1; #2 v2 = v1 + 1; #2 v2 = v1 + 1; v3 = v2 + 1; v3 = v2 + 1; #2 v4 = v3 + 1; #2 v4 = v3 + 1; v1 = v4 + 1; v1 = v4 + 1; #2 v2 = v1 + 1; #2 v2 = v1 + 1; v3 = v2 + 1; v3 = v2 + 1; end end What values does each block produce? 4
5. initial Blocks `timescale 1ns /1ns module t_full_adder; all initial blocks reg [3:0] stim; start at time 0 wire s, c; // instantiate UUT full_adder(sum, carry, stim[2], stim[1], stim[0]); // monitor statement is special - only needs to be made once, initial $monitor(“%t: s=%b c=%b stim=%b”, $time, s, c, stim[2:0]); // tell our simulation when to stop initial #50 $stop; single-statement block initial begin // stimulus generation for (stim = 4’d0; stim < 4’d8; stim = stim + 1) begin #5; end multi-statement block end enclosed by begin and endmodule end 5
6. always Blocks • Operates continuously or on a trigger list • Can be used with initial blocks • Cannot “nest” initial or always blocks • Useful example of continuous always block: reg clock; initial clock = 1’b0; always #10 clock = ~clock; • Clock generator goes in the testbench 6
7. always blocks with trigger lists • Conditionally “execute” inside of always block – Always block continuously operating – If trigger list present, continuously checking triggers – Any change on trigger (sensitivity) list, triggers block always @(a, b, c) begin end • Sounds like software! It isn’t! – This is how the simulator treats it – The hardware has the same resulting operation, but • See examples in later slides to see what is actually created 7
8. Trigger Lists • Uses “event control operator” @ • When net or variable in trigger list changes, always block is triggered always @(a, b, c) begin a1 = a & b; always @(state, input) begin a2 = b & c; if (input == 1’b0) begin a3 = a & c; if (state != 2’b11) carry = a1 | a2 | a3; nextstate = state + 1; end else nextstate = 2’b00; always @(in1, in0, sel) begin end else if (sel == 1’b0) out = in0; nextstate = state; else out = in1; end end 8
9. Event or • Original way to specify trigger list always @ (X1 or X2 or X3) • In Verilog 2001 can use , instead of or always @ (X1, X2, X3) • Verilog 2001 also has * for combinational only always @ (*) – Shortcut that includes all nets/variables used on RHS in statements in the block – Also includes variable used in if statements; if (x) • You may be asked to specify inputs to trigger list without * 9
10. Example: Comparator module compare_4bit_behave(output reg A_lt_B, A_gt_B, A_eq_B, input [3:0] A, B); 10
11. Solution: Comparator module compare_4bit_behave(output reg A_lt_B, A_gt_B, A_eq_B, input [3:0] A, B); always@( ) begin end endmodule 11
12. Edge Triggering • A negedge is on the transitions – 1 -> x, z, 0 – x, z -> 0 • A posedge is on the transitions – 0 -> x, z, 1 – x, z -> 1 • Used for clocked (synchronous) logic Different assignment always @ (posedge clk) operator! register <= register_input; 12
13. Example: DFF module dff(output reg q, input d, input clk); always @(posedge clk) begin q <= d; end endmodule module dff_reset(output reg q, input d, clk, reset); always @(posedge clk, negedge reset) begin if (!reset) q <= d; else q <= 0; end endmodule Why is q of type reg? 13
14. DFF with Set Control module dff(output q, qbar, input reset, set, data, clk); reg ; always @(posedge clk) begin . end endmodule 14
15. Procedural Assignments • Used within a behavioral block (initial, always) • Types – = // blocking assignment – <= // non-blocking assignment • Assignments to variables: – reg – integer – real – realtime – time 15
16. Blocking Assignments • “Evaluated” sequentially • Works a lot like software (danger!) • Used for combinational logic module addtree(output reg [9:0] out, input [7:0] in1, in2, in3, in4); reg [8:0] part1, part2; in1 in2 in3 in4 always @(in1, in2, in3, in4) begin part1 = in1 + in2; + + part2 = in3 + in4; out = part1 + part2; part1 part2 end endmodule + out 16
17. Non-Blocking Assignments • “Updated” simultaneously if no delays given • Used for sequential logic module swap(output reg out0, out1, input rst, clk); always @(posedge clk) begin D Q if (rst) begin out0 out0 <= 1’b0; rst rst to 0 out1 <= 1’b1; clk end else begin out0 <= out1; D Q out1 <= out0; out1 end rst to 1 end endmodule 17
18. Swapping • In blocking, need a “temp” variable module swap(output reg out0, out1, input in0, in1, swap); reg temp; always @(*) begin out0 = in0; in0 out1 = in1; in1 out0 if (swap) begin temp = out0; swap out0 = out1; out1 = temp; out1 end end endmodule 18
19. Blocking & Non-Blocking Example reg [7:0] A, B, C, D; reg [7:0] A, B, C, D; always @(posedge clk) always @(posedge clk) begin begin A = B + C; A <= B + C; B = A + D; B <= A + D; C = A + B; C <= A + B; D = B + D; D <= B + D; end end • Assume initially that A=1, B=2, C=3, and D=4 • Note: shouldn’t use blocking with sequential! 19
20. Correcting The Example reg [7:0] A, B, C, D; reg [7:0] newA, newB, newC, reg [7:0] A, B, C, D; newD; always @(posedge clk) always @(posedge clk) begin begin A <= B + C; A <= newA; B <= newB; B <= B + C + D; C <= newC; D <= newD; C <= B + C + B + C + D; end D <= B + C + D + D; always @(*) begin end newA = B + C; newB = newA + D; newC = newA + newB; newD = newB + D; end 20
21. Why Not ‘=‘ In Sequential? • Yes, it can “work”, but – <= models pipeline stages better – = can cause problems if multiple always blocks – Order of statements is important with = • Use the style guidelines given! – <= for sequential block – = for combinational block – Don’t mix in same block! 21
22. Shift Register: Blocking module shiftreg(E, A, clk, rst); output A; input E; input clk, rst; reg A, B, C, D; always @ (posedge clk or posedge rst) begin if (rst) begin A = 0; B = 0; C = 0; D = 0; end else begin A = B; B = C; C = D; D = E; end // option 1 // else begin D = E; C = D; B = C; A = B; end // option 2 end endmodule • What do we get with each option? 22
23. Shift Register: Blocking E A D Q R clk rst the order matters! E D C B A D Q D Q D Q D Q R R R R clk rst 23
24. Combinational vs. Sequential • Combinational – Not edge-triggered – All “inputs” (RHS nets/variables) are triggers – Does not depend on clock • Sequential – Edge-triggered by clock signal – Only clock (and possibly reset) appear in trigger list – Can include combinational logic that feeds a FF or register 24