Integrated On-Silicon and On-glass Antennas for mm-Wave Applications

Nội dung text: Integrated On-Silicon and On-glass Antennas for mm-Wave Applications

1. 8 REV Journal on Electronics and Communications, Vol. 11, No. 1–2, January–June, 2021 Invited Article Integrated On-Silicon and On-glass Antennas for mm-Wave Applications Nguyen Ngoc Mai-Khanh1, Tetsuya Iizuka1,2, Kunihiro Asada3 1 Systems Design Lab (d.lab), The University of Tokyo, Japan 2 Department of Electrical Engineering and Information Systems, The University of Tokyo, Japan 3 Emeritus Professor, The University of Tokyo, Japan Correspondence: Nguyen Ngoc Mai-Khanh, khanh@silicon.u-tokyo.ac.jp Communication: received 6 April 2021, revised 15 April 2021, accepted 15 April 2021 Online publication: 4 June 2021, Digital Object Identifier: 10.21553/rev-jec.267 The associate editor coordinating the review of this article and recommending it for publication was Prof. Vo Nguyen Quoc Bao. Abstract– The paper presents several integrated high frequency antenna prototypes based on Silicon (Si) CMOS and on-glass technologies for millimeter-wave (mm-wave) applications. An on-chip loop antenna and dipole radiator are presented. In addition, a wide-band dipole-patch antenna design for the range of 74 – 104 GHz is integrated into a CMOS chip with an on-chip pulse generator. In addition, an implementation of a fully on-Silicon antenna array integrated with a timed-array transmitter is introduced. To control the beam-forming of this array, a digital time adjustment circuit is integrated together with the antenna array. Simulated and measured data including return loss, and radiation patterns are presented. This paper also introduces an on-glass antenna prototypes fabricated on quartz substrate. The on-glass antenna is to demonstrate for handset or automobile’s windshield/windows applications where radio waves could be transmitted and received from various directions. The results show several compact antenna candidates integrated on both Si and quartz substrates towards mm-Wave/sub-mm-Wave sensing and communication applications. Keywords– antenna, mm-wave, on-chip, quartz, on-glass, integrated, array, CMOS, BiCMOS, calibration 1 Introduction very small area for getting high system performance and for reducing significantly size, cost and power. Nowadays, the evolution to high-speed cellular com- Antenna integration with its integrated system is an munication requires a completed integration of a mm- attractive topic due to the benefits of scaling and the wave/sub-mm-wave system including passive compo- possibility of integrating the digital backbone with the nents, active circuits, and even multiple antennas into RF front-end. The specific features of CMOS technology a small chip. Realizing such integrated antenna system process and its plenty of process design rules such requires significant challenges such as form factor, low- as metal path spacing, number of metal layers, angle power consumption, wide bandwidth, etc. for RF front for metal path, and metal density etc. limit antenna end. Integrated antenna bandwidth is very important and antenna array categories to be integrated. On-chip for the whole mm-wave system which requires critical antenna implementation is considered carefully based broadband and high Gbps data rates in 5G applications not only on antenna’s size, operating frequency and such as high resolution radar imaging or cellular com- specific applications but also on the fabrication process. munication. In recent years there has been an increasing In addition, this paper will deliberate some antenna interest in mm-wave/sub-mm-wave antennas design, candidates to be integrated into a chip and form an inte- integration, and measurement. Although antenna in- grated antenna array. Several constraints related to on- tegration confronts losses from the low-resistivity of chip antenna array implementation will be presented. Si-substrate and other interference [1], antenna array From the analysis of these requirements for integrating implementation enhances radiated power, reduce in- antenna array into a Si-based chip, designers can decide terconnections between on-chip RF circuit and off-chip suitable array’s parameters and necessary design trade- antennas, and provides a controllability of the array’s off for mm-wave applications. beam-forming for communication, sensing and imaging In this paper, several challenges for integrating anten- purposes nas into a chip are discussed. In addition, the paper will The smaller wavelength at millimeter-wave frequency review several on-chip antenna design on Si-substrate leads to higher free-space path loss; however, it also and also presents our latest results of on-glass antenna facilitates small-size high-gain antenna design, which design and measurement. The article is organized as can be used to compensate for the loss. By using follows. Section 2 introduces several challenges for Silicon technologies, completely integrated high fre- antenna integration in mm-wave frequency regime. In quency systems including inductors, capacitors, anten- Section 3, on-Si antenna and antenna array imple- nas and other RF components can be integrated in a mentation are presented. On-glass antenna fabrication 1859-378X–2021-1202 â 2021 REV
2. N. N. Mai-Khanh et al.: Integrated On-Silicon and On-glass Antennas for mm-Wave Applications 9 Antenna Types: and measurement are shown in Section 4. The paper conclusions are drawn in Section 5. how to integrate into a chip? 2 Challenges for Antenna Integration in High Frequencies Cross-section of a chip There are several important factors to determine a suit- able antenna operating in mm-wave frequency range to be integrated into a chip such as operating frequency, bandwidth B, directivity, gain, half-power beam-width (HPBW) and radiation efficiency. However, the mostly Figure 1. Antenna types and challenges to integrate into a chip. important parameters for antenna designers are B and efficiency. In mm-wave frequencies, antenna perfor- mance at center frequency f0 depends on relative band- has no back-lobe [4]. Therefore, the decision for an width B/ f0 and the antenna size becomes small as its integrated antenna will be made based on its suitable size is often proportional with the wavelength, λ, about shape, form-factor, termination configuration, and ra- λ/2 or λ/4, [1]. The mm-wave regime corresponds diation pattern. to a frequency range between 30 to 300 GHz or to Moreover, the substrate material underneath inte- correspond to free space wavelengths between 10 and grated antennas poses another challenges to be con- 1 mm. Therefore, antenna integration into a chip is sidered. In Si technologies, the Si substrate has a high possible in mm-wave frequency regime but with many permittivity and that reduces on-chip antenna dimen- challenges not only for antenna bandwidth, efficiency sion which is inversely proportional to the square root but also for antenna size, geometry, losses, and others. of the effective permittivity [1]. However, the larger There are various types of antennas for many appli- permittivity of the substrate (for example, e = 11.7) cations with different shapes and sizes as illustrated compared with air’s permittivity (e = 1) causes the in Figure 1 such as dipole, patch, parabolic, horn, etc. back-lobe of the on-chip antenna to be larger than the However, there are only several antenna types that can front-lobe [4] and most of its radiated power comes out be integrated into a chip. In a Si-technology-based inte- to the Si-substrate. In addition, the resistivity of the Si- grated circuit like CMOS or BiCMOS, there are plenty substrate is low and hence causes high loss and low of process design rules, such as spacing between metals, antenna efficiency. The solution to avoid the back-lobe metal width and thickness, angle for metal path, or radiation of an on-chip antenna is to additionally place antenna rules, etc. and that limits the on-chip antenna a metallic ground (GND) plane or mesh underneath the category to be designed. For example, it is impossible to antenna. This solution may reduce the back-lobe radi- implement on-chip horn antennas or parabolic shaped ation of the antenna, however requires much effort to antennas because their shape is incompatible with stan- design the GND plane to meet the constraints imposed dard CMOS process’ metal planar structures. Although by the process technology, especially for density rules, there are many general shapes of micro-strip patch electrical rule check (ERC), and design rule checking antennas, only a few shapes are suitable for integrating (DRC) errors. Furthermore, the substrate beneath on- into a chip, such as square, rectangular, dipole, circular, chip antennas may limit the antenna directivity. To triangle, etc. improve directivty, back-side removal methods such as For integrating a loop antenna into a chip, a loop etching the substrate underneath the antenna can be antenna in mm-wave frequencies can have small size applied with additional costs [5]. due to the corresponding wavelength. Several inte- The effect of packaging methods on integrated an- grated loop antennas are successfully integrated and tennas needs to be considered. Packaging works in- located at the perimeter of the chip [2, 3]. In several clude molding, shielding, and bonding. Bonding-wires applications requiring far-field radiations perpendic- connected to the antenna inputs can be in several mil- ularly to the chip’s surface loop antenna may not a limeters in length and that will introduce considerable compatible candidate to be integrated into a single chip. parasitic inductance to the antenna input as in mm- The maximum radiated direction or the directivity of wave frequency regime, the wavelength values varies loop antennas is on the same horizontal plane of the between 1 and 10 mm in the air and are comparable loop and hence the chip’s bonding-wires and package with these bonding-wires. The additional parasitic in- can resist, scatter, or even degrade the main radiation ductance can corrupt the impedance matching at the beam. antenna input and hence degrade the antenna perfor- Integrating an antenna into a Si chip also confronts mance. To avoid such effects of long bonding wires, losses from the low-resistivity of Si-substrate and other wire bond compensation techniques are used [6] or interference. The back-lobe of the far-field radiation flip-chip packaging techniques can be applied. With in case of no ground plane is much larger than the the use of solder balls, flip-chip packaging technique front-lobe and most of the antenna’s power radiates significantly reduces inductance connected to antenna backward to the Si-substrate, while the on-chip with- inputs [7–9]. Furthermore, the chip in which anten- ground-plane antenna radiates its power to the air and nas are integrated can be placed into a cavity by a
3. 10 REV Journal on Electronics and Communications, Vol. 11, No. 1–2, January–June, 2021 1840 um Figure 2. Loop antenna is operated as an inductor and integrated into a Si-Ge BiCMOS chip [10]. 290 um packaging method. However, this cavity may be closed on-chip PADs by a lid which will limit the antenna’s radiation pattern. (a) Dipole antenna integration into a Si chip in a meandering shape to reduce long arms 3 On-Silicon Antenna and Array Design Simulated linear polarization E_co There are several commonly used antenna types: slot 9 antenna, loop antenna, micro-strip patch antenna, or E_cross -1 dipole antenna that can be integrated into a chip. The -11 high permittivity of Si materials in CMOS technology -21 enables to reduce on-chip antenna dimension which is -31 inversely proportional to the square root of the effective -41 permittivity of the surrounding environment. However, the usage of low resistivity Si substrate causes high -51 loss and low antenna efficiency. A loop antenna is [dB] Mag. designed to employ its impedance for forming an R-L- C generating damping circuit and then is fabricated in a 2.5-V 0.25-àm 4-metal-layer SiGe BiCMOS process [10]. The loop antenna is small and located on the top metal as shown in Figure 2. Its resistance value is small, 3 Ω, Theta,θ, [-90:90] and hence the radiation may not be enough for the (b) Simulation and measurement results target of mm-wave sensing application. The challenge coming from the small resistance value of the loop Figure 3. Integrated meandering dipole antenna on 180 nm CMOS antenna can be solved by using a large loop radiator process and simulation results. array to form high radiating power and beam-forming capabilities. However, for the loop antenna choice, the maximum radiated direction of a loop antenna is the main challenge as it is on the antenna’s plane and also dipole antenna’s arms are in meandering shape and on the chip surface whose bonding-wires and package placed on the top metal of a 180 nm CMOS process can resist and scatter the main radiation beam. technology. As dipole terminal is balanced, a differ- Patch and dipole antennas offer different radiation ential GSGSG pad is added for probing measurement. directions and have several advantages compared with Figure 3(b) shows simulated and measured results of its loop antennas. Their maximum radiations are mainly linear polarization and S11. A de-embedding method perpendicular to the plane of antennas. Patch antenna using "open", "short", and "through" patterns is applied can eliminate back lobe due to the backside ground in the S-parameter measurement to remove substrate plane; which offers electric-magnetic benefits for form- coupling and contact effects. However, the measured ing antenna array. However, it is just suitable for un- S11 is positive at around the frequency range from 15– balanced feeding device; and requires a large metallic 24 GHz and this phenomenon may be from the reflec- plane underneath which can violate layout design rules tion and the coupling of the probe tips and the dipole. in Silicon technologies. In contract, dipole antenna re- The dipole is also integrated with a pulse generator quires balanced feeding termination and can overcome (PG) into a chip for time-domain measurement. process design rules. Nevertheless, dipole antenna has The measurement setup, depicted in Figure 5(a), radiated back lobes and requires long arms as shown employs a 10–15 GHz 20-dB standard horn antenna, in Figure 3. which is place perpendicular to the chip at a distance of 38 mm is connected to a sampling oscilloscope. The 3.1 On-chip Dipole Antenna received pulse signal is 1.1 mV peak-peak (p-p) with the Figure 3 presents a solution to shorten the long frequency response is 9–11 GHz, good matching with arm requirement of integrated dipole antenna [11]. The the dipole’s S11.
4. N. N. Mai-Khanh et al.: Integrated On-Silicon and On-glass Antennas for mm-Wave Applications 11 S11 of the on-Si meandering dipole antenna LW = 30 μm 10 625 μm 395 μm Top metal 0 30 μm -10 x=1μm S11 [dB] -20 measured metal 2 metal 1 simulated -30 Ground mesh 0 5 10 15 2025 30 Frequency [GHz] 5μm Figure 4. S11 simulation and measurement results of the on-Si dipole 5μm antenna. Figure 6. Dipole-patch antenna integration into a Si chip with a GND mesh. Simulated S11 of the dipole-patch antenna 0 BW = 30.21 GHz -5 -1 0 -1 5 S11, [dB] S11, -2 0 -2 5 -3 0 (a) Measurement setup using a standard horn antenna placed at a 40 60 80 100 120 140 160 distance from the chip freq. [GHz ] (a) Simulation of S11 of the antenna results Electric Far Field Normalize [dB] [degree] (b) Simulation of 3D radiation pattern results (b) Measured pulse waveform at the output of the standard horn 90 –140 -GHz standard y z = -23o HPBW = 9o antenna results horn antenna sec o o = 0 max_hor = 17 -30o 30o z Meas. limitation Figure 5. Measurement results of the meandering dipole antenna. x Meas. limitation @ 66 o -60o 60o = 0o Step motor 3.2 On-chip Dipole-Patch Antenna with Ground -90o 90o x 1 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1 Mesh (c) Measurement setup and radiation pattern results Most of the radiated power of an integrated dipole antenna comes out to the Si-substrate due to the large Figure 7. Integrated meandering dipole antenna on 65 nm CMOS permittivity of silicon substrate (ee f f = 11.7) compared process and measurement results. with air permittivity (eair = 1). This back-lobe radiation phenomenon can be avoided by using a back ground (GND) plane underneath the dipole or by using a radiation. The metal ground plane can be located in the patch antenna. A ground plane or ground mesh placed lowest metal layer while the antenna is at the topmost underneath the dipole radiator is to reflect radiated metal layer. Figure 7 shows an integrated antenna with power back to the air to avoid such undesired big back a mesh GND plane in our previous work [4].
5. 12 REV Journal on Electronics and Communications, Vol. 11, No. 1–2, January–June, 2021 This antenna is a combination of dipole and patch radiator types and is integrated into a 65 nm CMOS process chip. To avoid metallic density rules of the process, the ground mesh underneath the on-chip an- tenna is made by using metal-1 and metal-2 layers. In addition, the mesh is used to shield active layers from antenna radiation from top-metal layer based on calculation from [12]. The operating bandwidth of the antenna is 74–104 GHz in simulation as shown in Figure 7(a). Electromagnetic simulation results of the on-chip antenna including radiation and polarization patterns are presented. In addition, the dipole-patch an- tenna is integrated with a PG into a chip to characterize its radiation patterns. The measurement setup employs (a) Calibration idea for antenna Array a 90–140 GHz standard horn antenna attached to a mm- wave Schottky diode as a detector. The PG output is connected to the antenna by an on-chip transformer. Measured radiation patterns as presented in Figure 7(c) show two main beams of the antenna, matching with the simulation one. 3.3 Integrated Antenna Array with On-chip Skew Calibration Technique Due to the small form-factor of integrated antennas as well as the chip-package limitation, radiation power of a single integrated antenna might not be high nor sufficient enough for some practical applications. To en- hance the required radiation and system performance (b) On-chip pulse skew calibration diagram for array antenna clock multiple antenna elements can be integrated into a chip inputs. to form an antenna array. Such a number of antenna elements or antenna array can provide a beam-forming Figure 8. On-chip pulse skew calibration diagram for array antenna. to focus the radiation signal towards a specific receiving device with controllable beam angles and beam-width, rather than having the signal spread in wide direc- process. An 8 element dipole antenna array with time tions from a single element. Beam-forming and beam- delay monitor & control circuit, meandering dipole scanning are performed by phasing the feed to each antenna, shock wave generator with this antenna and element of an array so that signals received or transmit- an on-chip jitter measuring circuit are integrated in this ted from all elements will be in phase in a particular chip for mm-wave shock wave transmitter system. direction. In mm-wave frequency regime, phase con- Each of dipole antenna is fed to output terminals of a trol and propagation delay of the signals required for shock wave generator or pulse generator (PG) through beamformability are in the range of sub nanoseconds or a transformer. The PG is implemented by employing even picoseconds. Therefore, integrated antenna array serial RLC circuit principle. In this chip, the PG is design in mm-wave frequencies gets more challenges designed to obtain output pulse with center frequency and issues than single radiator integration one. of 100-GHz and minimum pulse delay of 1-ps. An 8- One of the challenges for integrating an mm-wave digitally programmable delay circuit supplies an ability antenna array into a single chip is to calibrate the prop- of pulse delay adjustment with 7-bit data input. More- agation delay of array elements. Phase or time-delay over, an on-chip jitter measuring circuit is added to the differences between array elements are very important circuit in order to monitor and adjust the pulse delay for beam-forming control. However, process variations as well as jitters by observing 20-bit data output values. in semiconductor including skews in time domain. The timed delay monitoring and controlling circuit for Depending on the fabrication process, the delay or skew the whole array system is also fabricated. variations can be up to several tens of picoseconds and The idea to adjust pulse delays between antenna that can cause inability to control the antenna array elements is developed from the wave to manually tune for beam-forming and beam-scanning which require guitar’s string without tuner. timing calibration for each array elements. Figure 8 describes the inverter chain buffer and the Figure 8(a) illustrates a functional block diagram ith pulse generator (PG) which employs the operation of an antenna array transmitter including pulse delay principle of serial RLC circuit, i = 0. . . 7. After changing monitor and control unit, on-chip jitter measuring cir- several values of QNi’s W/L ratio as the same proce- cuit, and debug block. This transmitter is integrated dure in Section 3.1 and based on estimation of power into a 2-mmì4-mm chip by using a 65-nm CMOS consumption, peak-peak pulse output, generated pulse
6. N. N. Mai-Khanh et al.: Integrated On-Silicon and On-glass Antennas for mm-Wave Applications 13 frequency, and chip area, a ratio of W/L = 8ì100- 3D Far-field Simulation of the Array Antenna àm/60-nm is determined for QNi and a small PMOS size of W/L = 2-àm/100-nm is chosen for QPi. The source (S) terminal of NMOS NM3 is not shorted to ground but connected to output terminal, VVARi of a digitally programmable delay circuit (DPDC) in order to adjust delays of clock signal VinQi and also of pulse output signal at antenna’s terminal. A simple binary-weighted current-steering DAC (Digital to Analog Converter) is used for controlling the current of variable delay elements which only affects driving current of the third inverter in Figure 8(b) to achieve precise resolution such as sub-picoseconds. Figure 8(b) presents a detailed diagram of RESC and a target variable delay line including a 7-bit DPDC and 4-inverter delay chain. By varying input vectors of Figure 9. Far field simulation of the 8-element array antenna in the DPDC, the current IVARi is changed and hence output case no phase difference between elements. pulse delays are achieved. This ability to adjust pulse delays is the requirement of wide-band antenna array operation principle for pulse beam-forming and steer- w/o calibration ing. Simulated result of the target variable delay line characteristics vs. input delay code in which minimum differential delay can be achieved at 0.1 ps. We introduced an on-chip calibration method for antenna array as illustrated in Figure 8(a) to perform an on-chip pulse alignment for all eight array’s elements which are fed into the outputs of 8 PGs [13, 14]. Eight clocks of antennas are distributed by a clock-tree layout to one clock input, ANTCLK. To perform the skew calibration, another clock is used as a reference one, (a) Radiation measurement results without skew calibration calibra- REFCLK. The principle of the skew calibration is based tion on the operating property of D-flip flop (F/F) when w/ calibration swapping two terminal CLK and D inputs of D-F/F then sweeping the delay of the other. Feeding line network is usually used to distribute signals to each antenna element for the desired beam- forming direction. For wide-band antenna array, clock tree structure, so-called feeding line clock network, is conventionally employed to ensure equally distributed micro-trip or transmission line paths to each antenna block. However, in high frequency-based antenna ar- rays, clock tree distribution method generates jitters and skew at terminals of target antenna blocks and and hence needs skew measurement and adjustment (b) Radiation measurement results with skew calibration calibration circuits or equipment. While jitters and skew mea- surements require special equipment with large output Figure 10. Radiation simulation and measurement results with and drivers, skew adjustments in some cases cannot be re- without on-chip pulse calibration. corrected after fabrication. At first, outputs of two target/reference VDLs are connected to D input and clock input of a D-FF, respec- The integrated 8-antenna array transmitter with 8 tively, and then a Cumulative Distribution Function, pulse generators and a pulse delay system to adjust on- CDF1, is obtained by scanning input code values of chip skew and pulse-delay was performed. The trans- the reference VDL. Next, output of the target VDL is mitter is an on-chip array of 8-dipole antennas with pro- changed to clock input of a D-FF while output of the grammable pulse-delay monitoring and controlling sys- reference VDL is connected to the same D-FF’s data tem. A digitally controllable pulse-array circuit is inte- input. Another CDF, CDF0 is drawn by sweep the input grated together with the antenna array to adjust on-chip code values. From the combination of these two func- relative pulses. Measured radiation pattern results illus- tions, CDF0 and CDF1, two D-FFs’ setup times is mea- trate beam-forming angles obtained versus input codes sured. If two D-FFs are same and symmetrical in struc- as shown in Figure 10. This result demonstrates that the ture, D-FF’s setup time measurement can be achieved antenna array transmitter can be digitally controlled for just by dividing the two D-FFs’ setup timing by 2. active imaging in medical diagnosis applications.
7. 14 REV Journal on Electronics and Communications, Vol. 11, No. 1–2, January–June, 2021 dipole antenna on-glass chip Aluminium, thickness = 3um 6 Acknowledgments The authors would like to thank the activities of Sys- SiO2 1 mm tems Design Center (d.lab), The University of Tokyo, Japan in collaboration with: Rohm Corporation, Toppan Printing Corporation, Synopsys, Inc., Cadence Design Glass substrate GSGSG probe Systems, Inc. and Agilent Technologies Japan, Ltd Figure 11. On-glass dipole antenna cross-section. This work is supported in part by JSPS KAKENHI Grant Number 21H03406. S-parameter measurement PNX setup Network Analyzer References [1] C. A. Balanis, Ed., Antenna Theory: Analysis and Design, 3rd ed. John Wiley & Son Inc., 2005. on-glass chip [2] E. Ojefors, H. Kratz, K. Grenier, R. Plana, and A. Ryd- GSGSG probe berg, “Micromachined loop antennas on low resistivity silicon substrates,” IEEE Transactions on antennas and SMA cables propagation, vol. 54, no. 12, pp. 3593–3601, 2006. Probe station [3] H. Schumacher, P. Abele, E. Sửnmez, K.-B. Schad, and A. Trasser, “Low-cost circuit solutions for micro-and millimeter-wave systems using commercially available SiGe technologies,” Applied surface science, vol. 224, no. 1-4, pp. 410–418, 2004. Figure 12. On-glass dipole antenna probing measurement. [4] N. N. M. Khanh, M. Sasaki, and K. Asada, “A millimeter- wave resistor-less pulse generator with a new dipole- patch antenna in 65-nm cmos,” Analog Integrated Circuits 4 On-Glass Antenna Design and and Signal Processing, vol. 73, no. 3, pp. 789–799, 2012. [5] N. N. Mai-Khanh, T. Iizuka, A. Sasaki, M. Yamada, Fabrication O. Morita, and K. Asada, “A near-field magnetic sens- ing system with high-spatial resolution and application For antenna designers, antenna substrate is a key for security of cryptographic lsis,” IEEE Transactions on parameter to consider because the substrate material Instrumentation and Measurement, vol. 64, no. 4, pp. 840– determines the antenna bandwidth, antenna loss, the 848, 2015. [6] S. Beer, C. Rusch, H. Gulan, B. Goettel, M. G. Girma, back reflector, back-lobe radiation, and the isolation J. Hasch, W. Winkler, W. Debski, and T. Zwick, “An mean between the antenna, feeder, and other RF related integrated 122-ghz antenna array with wire bond com- components. In several applications where transmits pensation for smt radar sensors,” IEEE Transactions on and receives through antenna substrate are re Antennas and Propagation, vol. 61, no. 12, pp. 5976–5983, To avoid the back-lobe radiation at large permittivity 2013. [7] A. Townley, P. Swirhun, D. Titz, A. Bisognin, F. Giane- Si-substrates, quartz or glass materials are used for the sello, R. Pilard, C. Luxey, and A. Niknejad, “A 94GHz antenna substrate. In addition, in some applications 4TX-4RX phased-array for FMCW radar with integrated where radio waves need to be transmitted and received LO and flip-chip antenna package,” in Proceedings of from various directions, on-glass antenna is applicable the IEEE Radio Frequency Integrated Circuits Symposium and suitable. This paper also introduces an on-glass (RFIC). IEEE, 2016, pp. 294–297. [8] E. Cohen, M. Ruberto, M. Cohen, O. Degani, S. Ravid, antenna prototypes fabricated on quartz substrates as and D. Ritter, “A CMOS bidirectional 32-element shown in Figure 11. The antenna is in dipole shape with phased-array transceiver at 60 GHz with LTCC antenna,” thick and large arms. A GSGSG pad is attached to the IEEE Transactions on Microwave Theory and Techniques, antenna terminals for probing measurement. The probe vol. 61, no. 3, pp. 1359–1375, 2013. lands to the GSGSG pad and connected to an Agilent [9] B.-H. Ku, O. Inac, M. Chang, H.-H. Yang, and G. M. Rebeiz, “A high-linearity 76–85-GHz 16-element 8- N5247A Network Analyzer to measure S11 values. The transmit/8-receive phased-array chip with high isolation measured operating frequency center of the antenna is and flip-chip packaging,” IEEE Transactions on Microwave at 14 GHz. The on-glass antenna is to demonstrate for Theory and Techniques, vol. 62, no. 10, pp. 2337–2356, 2014. handset or automobile’s windshield/windows applica- [10] N. N. M. Khanh, M. Sasaki, and K. Asada, “A 0.25- tions. àm Si-Ge Fully Integrated Pulse Transmitter with On- Chip Loop Antenna Array towards Beam-Formability for Millimeter-Wave Active Imaging,” IEICE transactions on electronics, vol. 94, no. 10, pp. 1626–1633, 2011. 5 Conclusion [11] ——, “A fully integrated shock wave transmitter with an on-chip dipole antenna for pulse beam-formability in This paper presents several integrated antenna designs 0.18-àm cmos,” in Proceedings of the 16th Asia and South and measurements in both Si-substrate and glass sub- Pacific Design Automation Conference (ASP-DAC 2011). strate. Experimental results show that the proposed on- IEEE, 2011, pp. 107–108. chip transceiver has an ability of digital transmitted- [12] N. G. Alexopoulos, P. B. Katehi, and D. B. Rutledge, “Substrate optimization for integrated circuit antennas,” pulse calibration and detection of beam-forming pulses IEEE Transactions on Microwave Theory and Techniques, not only for communications but also active imaging or vol. 31, no. 7, pp. 550–557, 1983. diagnosis applications. [13] N. N. M. Khanh and K. Asada, “A CMOS fully
8. N. N. Mai-Khanh et al.: Integrated On-Silicon and On-glass Antennas for mm-Wave Applications 15 integrated antenna system transceiver with beam- Tetsuya Iizuka received the B.S., M.S., and formability for millimeter-wave active imaging,” in Pro- Ph.D. degrees in electronic engineering from ceedings of the IEEE 13th Topical Meeting on Silicon Mono- the University of Tokyo, Tokyo, Japan, in 2002, lithic Integrated Circuits in RF Systems. IEEE, 2013, pp. 2004, and 2007, respectively. 123–125. From 2007 to 2009, he was with THine Electronics Inc., Tokyo, Japan, as a high-speed [14] N. N. M. Khanh, M. Sasaki, and K. Asada, “A 65-nm serial interface circuit engineer. He joined the CMOS fully integrated shock-wave antenna array with University of Tokyo in 2009, where he is cur- on-chip jitter and pulse-delay adjustment for millimeter- rently an Associate Professor with Systems wave active imaging application,” IEICE Transactions on Design Lab., School of Engineering. From 2013 Fundamentals of Electronics, Communications and Computer to 2015, he was a Visiting Scholar with the Sciences, vol. 94, no. 12, pp. 2554–2562, 2011. University of California, Los Angeles, CA, USA. His current research interests include data conversion techniques, high-speed analog inte- grated circuits, digitally-assisted analog circuits and VLSI computer- aided design. Dr. Iizuka is a member of the Institute of Electronics, Information and Communication Engineers (IEICE). He was a member of the IEEE International Solid-State Circuits Conference (ISSCC) Technical Program Committee from 2013 to 2017 and a member of the IEEE Custom Integrated Circuits Conference (CICC) Technical Program Committee from 2014 to 2019. From 2016 to 2018, he served as the Editor of IEICE Electronics Express (ELEX). He is currently serving as a member of the IEEE Asian Solid-State Circuits Conference (A- Nguyen Ngoc Mai-Khanh was born in Vung SSCC) Technical Program Committee. Tau city, Viet Nam. He received the B.S. and He was a recipient of the Young Researchers Award from IEICE M.S. degrees in Electrical Engineering from in 2002, the IEEE International Conference on Electronics, Circuits the University of Technology, National Uni- and Systems Best Student Paper Award in 2006, the Yamashita SIG versity, HoChiMinh city (HCMC), Vietnam, Research Award from the Information Processing Society, Japan in in 2002 and 2004, respectively, and Ph.D. de- 2007, the 21st Marubun Research Encouragement Commendation gree in Electrical Engineering and Information from Marubun Research Promotion Foundation in 2018, the 13th Systems, the University of Tokyo, Japan in Wakashachi Encouragement Award First Prize in 2019 and the 18th 2011. During January 2006 to June 2006, he Funai Academic Prize from Funai Foundation for Information Tech- joined a short-term project for the internship nology in 2019. He was a co-recipient of the IEEE International Test in Toshiba R&D, Kawasaki, Japan. He was Conference Ned Kornfield Best Paper Award in 2016. a Lecturer of Faculty of Electrical and Electronic Engineering, the University of Technology, National University, Viet Nam from 2006 to 2013. Dr. Mai-Khanh worked as a post-doctoral researcher in VLSI Design and Education Center (VDEC), the University of Tokyo, Japan from 2011 to 2013 and currently is an Assistant Professor at Systems Kunihiro Asada was born in Fukui, Japan, Design Lab., The University of Tokyo, Japan. In 2019, he was a Visiting 1952. He received the B. S., M. S., and Ph.D. Scholar with Eindhoven University of Technology, Eindhoven, Hol- in electronic engineering from University of land. His current research interests include integrated analog circuits, Tokyo in 1975, 1977, and 1980, respectively. millimeter-wave circuits, on-chip antennas, and integrated magnetic In 1980 he joined the Faculty of Engineering, sensing. University of Tokyo, and became a lecturer, Dr. Mai-Khanh is currently a member of IEEE. He is a recipient of an associate professor and a professor in 1981, the Best Paper Award of the Asian Symposium on Quality Electronic 1985 and 1995, respectively. From 1985 to 1986 Design Symp. in 2010, the third rank of the Best Student Paper Award he stayed in Edinburgh University as a visit- of the 9th IEEE NEWCAS 2011, and co-recipient of the Best Paper ing scholar supported by the British Council. Award of IEEE NEWCAS 2017. He has served as a reviewer on IEEE From 1990 to 1992 he served as the first Editor Journal of Sensor, IEEE Microwave and Wireless Components Letters, of English version of IEICE (Institute of Electronics, Information and IEEE Trans. on Instrumentation and Measurement (TIM), Springer Communication Engineers of Japan) Transactions on Electronics. In Journal of Analog Integrated Circuits and Signal Processing, and 1996 he established VDEC (VLSI Design and Education Center) with Electronic Letters of Institution of Engineering and Technology (IET). his colleagues in University of Tokyo, which is a center to promote He was the chair of Technical Program Committee (TPC) of Vietnam- education and research of VLSI design in all the universities and Japan Scientific Exchange Meeting 2017 and a TPC member of Intl. colleges in Japan. He also served as the Chair of IEEE/SSCS Japan Conf. on Integrated Circuits, Design, and Verification (ICDV) 2017. Chapter in 2001-2002 and the Chair of IEEE Japan Chapter Operation Committee in 2007-2008. He is currently in charge of the director of VDEC. His research interest is design and evaluation of integrated systems and component devices. He has published more than 400 technical papers in journals and conference proceedings. He has received best paper awards from IEEJ (Institute of Electrical Engineers of Japan), IEICE and ICMTS1998/IEEE and so on. He is a member of IEEE, IEICE and IEEJ.